VHDL重的testbeach文件写法

弄了好长时间vhdl，一直对testbench很迷惑。前几天静下心来好好看了下资料，终于会写简单的testbench了。

六进制计数器的代码

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1. library ieee;

2. use ieee.std_logic_1164.all; 3. use ieee.std_logic_arith.all; 4. --use ieee.std_logic_unsigned.all; 5.

6. entity cnt6 is 7. port

8. (clr,en,clk :in std_logic;

9. q :out std_logic_vector(2 downto 0) 10. ); 11. end entity; 12.

13. architecture rtl of cnt6 is

14. signal tmp :std_logic_vector(2 downto 0); 15. begin

16. process(clk)

17. -- variable q6:integer; 18. begin

19. if(clk'event and clk='1') then 20. if(clr='0')then 21. tmp<=\; 22. elsif(en='1') then 23. if(tmp=\)then 24. tmp<=\; 25. else

26. tmp<=unsigned(tmp)+'1'; 27. end if; 28. end if; 29. end if; 30. q<=tmp; 31. -- qa<=q(0); 32. -- qb<=q(1); 33. -- qc<=q(2); 34. end process; 35. end rtl;

六进制计数器testbench的代码

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1. library ieee;

2. use ieee.std_logic_1164.all; 3.

4. entity cnt6_tb is 5. end cnt6_tb; 6.

7. architecture rtl of cnt6_tb is 8. component cnt6 9. port(

10. clr,en,clk :in std_logic;

11. q :out std_logic_vector(2 downto 0) 12. );

13. end component; 14.

15. signal clr :std_logic:='0'; 16. signal en :std_logic:='0'; 17. signal clk :std_logic:='0';

18. signal q :std_logic_vector(2 downto 0); 19.

20. constant clk_period :time :=20 ns; 21. begin

22. instant:cnt6 port map 23. (

24. clk=>clk,en=>en,clr=>clr,q=>q 25. );

26. clk_gen:process 27. begin

28. wait for clk_period/2; 29. clk<='1';

30. wait for clk_period/2; 31. clk<='0'; 32. end process; 33.

34. clr_gen:process 35. begin 36. clr<='0'; 37. wait for 30 ns; 38. clr<='1';

39. wait; 40. end process; 41.

42. en_gen:process 43. begin 44. en<='0'; 45. wait for 50ns; 46. en<='1'; 47. wait; 48. end process; 49. end rtl;

其实testbench也有自己固定的一套格式，总结如下：

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1. --测试平台文件(testbench)的基本结构 2. library ieee;

3. use ieee.std_logic_1164.all; 4.

5. entity test_bench is --测试平台文件的空实体（不需要端口定义) 6.

7. end test_bench; 8.

9. architecture tb_behavior of test_bench is

10. component entity_under_test --被测试元件的声明 11. port(

12. list-of-ports-theri-types-and-modes 13. );

14. end component; 15. 16. begin

17. instantiation:entity_under_test port map 18. (

19. port-associations 20. ); 21.

22. process() --产生时钟信号 23. ……

24. end process; 25.

26. process() --产生激励源

27. ……

28. end process; 29. end tb_behavior; 30.

31. ------------------------------------------------------------------- 32. --简单计数程序源码 33. library ieee;

34. use ieee.std_logic_1164.all; 35. use ieee.std_logic_unsigned.all; 36. use ieee.std_logic_unsigned.all; 37.

38. entity sim_counter is 39. port(

40. clk :in std_logic; 41. reset :in std_logic;

42. count :out std_logic_vector(3 downto 0) 43. ); 44. end entity; 45.

46. architecture behavioral of sim_counter is 47.

48. signal temp :std_logic_vector(3 downto 0); 49. 50. begin

51. process(clk,reset) 52. begin

53. if reset='1' then 54. temp<=\;

55. elsif clk'event and clk='1' then 56. temp<=temp+1; 57. end if; 58. end process; 59. count<=temp; 60. end behavioral; 61.

62. ------------------------------------------------------------------- 63. --简单计数程序，测试文件代码(testbench) 64. library ieee;

65. use ieee.std_logic_1164.all; 66. use ieee.std_logic_unsigned.all; 67. use ieee.numeric_std.all; 68.

69. entity counter_tb_vhd is --测试平台实体 70. end counter_tb_vhd;