Package Overview
Table81 shows the 10 low-cost, space-saving production package styles for the Spartan-3 family. Each package style is available as a standard and an environmentally-friendly lead-free (Pb-free) option. The Pb-free packages include an extra ‘G’ in the package style name. For example, the standard \Pb-free option. The mechanical dimensions of the standard and Pb-free packages are similar, as shown in the mechanical drawings provided in Table83.
Not all Spartan-3 device densities are available in all packages. However, for a specific package there is a common footprint that supports the various devices available in that package. See the footprint diagrams that follow.Table 81:Spartan-3 Family Package Options
PackageVQ100 / VQG100CP132 / CPG132(1)TQ144 / TQG144PQ208 / PQG208FT256 / FTG256FG320 / FGG320FG456 / FGG456FG676 / FGG676FG900 / FGG900FG1156 / FGG1156(1)
Leads1001321442082563204566769001156
Type
Very-thin Quad Flat PackChip-Scale PackageThin Quad Flat PackQuad Flat Pack
Fine-pitch, Thin Ball Grid ArrayFine-pitch Ball Grid ArrayFine-pitch Ball Grid ArrayFine-pitch Ball Grid ArrayFine-pitch Ball Grid ArrayFine-pitch Ball Grid Array
Maximum
I/O
638997141173221333489633784
Pitch (mm)0.50.50.50.51.01.01.01.01.01.0
Footprint(mm)16 x 168 x 822 x 2230.6 x 30.617 x 1719 x 1923 x 2327 x 2731 x 3135 x 35
Height (mm)1.201.101.604.101.552.002.602.602.602.60
Notes: 1. The CP132, CPG132, FG1156, and FGG1156 packages are discontinued. See .
Selecting the Right Package Option
Spartan-3 FPGAs are available in both quad-flat pack (QFP) and ball grid array (BGA) packaging options. While QFP
packaging offers the lowest absolute cost, the BGA packages are superior in almost every other aspect, as summarized in Table 82. Consequently, Xilinx recommends using BGA packaging whenever possible.Table 82: Comparing Spartan-3 Device Packaging Options
Characteristic
Maximum User I/O
Packing Density (Logic/Area)Signal Integrity
Simultaneous Switching Output (SSO) SupportThermal Dissipation
Minimum Printed Circuit Board (PCB) LayersHand Assembly/Rework
Quad Flat-Pack (QFP)
141GoodFairLimitedFair4Possible
Ball Grid Array (BGA)
633BetterBetterBetterBetter6Very Difficult
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
Table 85:Maximum User I/Os by Package
DeviceXC3S50XC3S200XC3S50XC3S50XC3S200XC3S400XC3S50XC3S200XC3S400XC3S200XC3S400XC3S1000XC3S400XC3S1000XC3S1500XC3S400XC3S1000XC3S1500XC3S2000XC3S1000XC3S1500XC3S2000XC3S4000XC3S5000XC3S2000XC3S4000XC3S5000XC3S4000XC3S5000
PackageVQ100VQ100CP132(1)TQ144TQ144TQ144PQ208PQ208PQ208FT256FT256FT256FG320FG320FG320FG456FG456FG456FG456FG676FG676FG676FG676FG676FG900FG900FG900FG1156(1)FG1156(1)
Maximum User I/Os
636389979797124141141173173173221221221264333333333391487489489489565633633712784
Maximum Differential Pairs
292944464646566262767676100100100116149149149175221221221221270300300312344
All Possible I/O Pins by Type
I/O222244515151728383113113113156156156196261261261315403405405405481549549621692
DUAL1212121212121212121212121212121212121212121212121212121212
DCI1414141414141616161616161616161616161616161616161616161616
VREF77111212121622222424242929293236363640484848484848485556
GCLK88888888888888888888888888888
N.C.0000001700000000690009820006800731
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Table92 indicates how the available user-I/O pins are distributed between the eight I/O banks on the TQ144 package.Table 92:User I/Os Per Bank in TQ144 Package
Package Edge
TopRightBottomLeft
I/O Bank
01234567
Maximum I/O
10914151191415
All Possible I/O Pins by Type
I/O541011001011
DUAL00006600
DCI22222022
VREF11221122
GCLK22002200
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
PQ208: 208-lead Plastic Quad Flat Pack
The 208-lead plastic quad flat package, PQ208, supports three different Spartan-3 devices, including the XC3S50, the XC3S200, and the XC3S400. The footprints for the XC3S200 and XC3S400 are identical, as shown in Table 93 and Figure 47. The XC3S50, however, has fewer I/O pins resulting in 17 unconnected pins on the PQ208 package, labeled as “N.C.” In Table 93 and Figure 47, these unconnected pins are indicated with a black diamond symbol (?).
All the package pins appear in Table 93 and are sorted by bank number, then by pin name. Pairs of pins that form a differential I/O pair appear together in the table. The table also shows the pin number for each pin and the pin type, as defined earlier.
If there is a difference between the XC3S50 pinout and the pinout for the XC3S200 and XC3S400, then that difference is highlighted in Table 93. If the table entry is shaded grey, then there is an unconnected pin on the XC3S50 that maps to a user-I/O pin on the XC3S200 and XC3S400. If the table entry is shaded tan, then the unconnected pin on the XC3S50 maps to a VREF-type pin on the XC3S200 and XC3S400. If the other VREF pins in the bank all connect to a voltage reference to support a special I/O standard, then also connect the N.C. pin on the XC3S50 to the same VREF voltage. This provides maximum flexibility as you could potentially migrate a design from the XC3S50 device to an XC3S200 or XC3S400 FPGA without changing the printed circuit board.
An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at
Pinout Table
Table 93:PQ208 Package Pinout
Bank00000000000000000011111
IOION.C. (?)IO/VREF_0IO_L01N_0/VRP_0IO_L01P_0/VRN_0IO_L25N_0IO_L25P_0IO_L27N_0IO_L27P_0IO_L30N_0IO_L30P_0IO_L31N_0IO_L31P_0/VREF_0IO_L32N_0/GCLK7IO_L32P_0/GCLK6VCCO_0VCCO_0IOIOIO
IO_L01N_1/VRP_1IO_L01P_1/VRN_1
XC3S50 Pin NameXC3S200, XC3S400
Pin NamesIOIO
IO/VREF_0IO/VREF_0IO_L01N_0/VRP_0IO_L01P_0/VRN_0IO_L25N_0IO_L25P_0IO_L27N_0IO_L27P_0IO_L30N_0IO_L30P_0IO_L31N_0IO_L31P_0/VREF_0IO_L32N_0/GCLK7IO_L32P_0/GCLK6VCCO_0VCCO_0IOIOIO
IO_L01N_1/VRP_1IO_L01P_1/VRN_1
PQ208 Pin NumberP189P197P200P205P204P203P199P198P196P194P191P190P187P185P184P183P188P201P167P175P182P162P161
TypeI/OI/OVREFVREFDCIDCII/OI/OI/OI/OI/OI/OI/OVREFGCLKGCLKVCCOVCCOI/OI/OI/ODCIDCI
DS099 (v3.1) June 27, 2013Product Specification
Spartan-3 FPGA Family: Pinout Descriptions
User I/Os by Bank
Table108 indicates how the available user-I/O pins are distributed between the eight I/O banks for the XC3S2000 in the FG900 package. Similarly, Table109 shows how the available user-I/O pins are distributed between the eight I/O banks for the XC3S4000 and XC3S5000 in the FG900 package.
Table 108:User I/Os Per Bank for XC3S2000 in FG900 Package
EdgeTopRightBottomLeft
I/O Bank
01234567
Maximum I/O
7171697172716971
All Possible I/O Pins by Type
I/O6262616257556062
DUAL00006600
DCI22222222
VREF55675677
GCLK22002200
Table 109:User I/Os Per Bank for XC3S4000 and XC3S5000 in FG900 Package
EdgeTopRightBottomLeft
I/O Bank
01234567
Maximum I/O
7979797980797979
All Possible I/O Pins by Type
I/O7070717065637070
DUAL00006600
DCI22222222
VREF55675677
GCLK22002200
DS099 (v3.1) June 27, 2013Product Specification
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