基于FPGA数字秒表设计(完整资料).doc

2.1.6显示电路

实验电路板上的按键

2.1.7按键消抖电路

消除按键输入信号抖动的影响，输出单脉冲

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按键按下时，FPGA的输入为低电平；松开按键时，FPGA的输入为高电平

但是在按下按键和松开按键的瞬间会出现抖动现象

2.2电路框图实验板上的数码管为共阳LED

数码管

3.电路实现

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-- Company: -- Engineer: --

-- Create Date: 09:08:39 03/12/2011 -- Design Name:

-- Module Name: stopwatch_1 - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: --

-- Dependencies: --

-- Revision:

-- Revision 0.01 - File Created -- Additional Comments: --

---------------------------------------------------------------------------------- library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM;

--use UNISIM.VComponents.all;

entity stopwatch_1 is Port (

Clk : in STD_LOGIC;

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start_stop : in STD_LOGIC; split_reset : in STD_LOGIC;

ncs : out STD_LOGIC;

s : out STD_LOGIC_VECTOR(2 downto 0); seg : out STD_LOGIC_VECTOR (7 downto 0) );

end stopwatch_1;

architecture Behavioral of stopwatch_1 is signal k1,k2,k3,k4: STD_LOGIC;

signal cnt_1,cnt_2 : STD_LOGIC_VECTOR(1 downto 0); signal start_stop_out,split_reset_out: STD_LOGIC;

signal count: STD_LOGIC_VECTOR(15 downto 0):=(others=>'0');

signal clk_1k: STD_LOGIC;

signal z0,z1,z2,z3,z4,z5,z6,q1,q2,q3,q4,q5,q6 :

STD_LOGIC_VECTOR(3 downto 0):=(others=>'0');

signal count_2: STD_LOGIC_VECTOR(2 downto 0 ):=(others=>'0');

signal in_7: STD_LOGIC_VECTOR(3 downto 0);

signal sreg: STD_LOGIC_VECTOR(2 downto 0):=\ signal snext: STD_LOGIC_VECTOR(2 downto 0); Begin

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