基于FPGA数字秒表设计(完整资料).doc

4.1.1计数器电路综合

4.1.2计数器电路仿真

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由图可得分频后的信号周期T=999333718ps≈0.001s 即的到了1KHz的信号

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由图可得时钟信号周期T=20845ps≈20.845ns 即的到了48MHz的时钟信号

4.2同步计数器 4.2.1计数器实现

entity count_6 is

Port ( clk_1k : in STD_LOGIC;

d1 : out STD_LOGIC_VECTOR(3 downto 0); d2 : out STD_LOGIC_VECTOR(3 downto 0);

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d3 : out STD_LOGIC_VECTOR(3 downto 0); d4 : out STD_LOGIC_VECTOR(3 downto 0); d5 : out STD_LOGIC_VECTOR(3 downto 0); d6 : out STD_LOGIC_VECTOR(3 downto 0)); end count_6;

architecture Behavioral of count_6 is

signal z0,z1,z2,z3,z4,z5,z6: STD_LOGIC_VECTOR(3 downto 0):=(others=>'0');

signal clr,en: STD_LOGIC;

Begin

clr <= '0'; ---------------------------------------------清零无效 en <= '1'; ---------------------------------------------计数使能有效

d1 <= z1; d2 <= z2; d3 <= z3; d4 <= z4; d5 <= z5; d6 <= z6;

process(clk_1k,clr) begin

if rising_edge(clk_1k) then if clr = '1' then

z0<=(others=>'0'); z1<=(others=>'0'); z2<=(others=>'0'); z3<=(others=>'0'); z4<=(others=>'0'); z5<=(others=>'0'); z6<=(others=>'0');

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