erased state (that is, contents = FFH) and ready to be programmed. The programming interface accepts either a high-voltage (12-volt) or a low-voltage (VCC) program enable signal. The low voltage programming mode provides a convenient way to program the at89s52 inside the user’s system, while the high-voltage programming mode is compatible with conventional third party Flash or EPROM programmers. The at89s52 is shipped with either the high-voltage or low-voltage programming mode enabled. The respective top-side marking and device signature codes are listed in the following table. Vpp=12v Vpp=5v Top-side at89s52 at89s52 mark xxxx xxxx-5 yyww yyww signature (030H)=1EH (030H)=1EH (031H)=51H (031H)=51H (032H)=FFH (032H)=05H The at89s52 code memory array is programmed byte-bybyte in either programming mode. To program any nonblank byte in the on-chip Flash Programmable and Erasable Read Only Memory, the entire memory must be erased using the Chip Erase Mode. Programming Algorithm: Before programming the at89s52, the address, data and control signals should be set up according to the Flash programming mode table and Figures 3 and 4. To program the at89s52, take the following steps. 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 4. Raise EA/VPP to 12V for the high-voltage programming mode. 5. Pulse ALE/PROG once to program a byte in the Flash array or the lock bits. The byte-write cycle is self-timed and typically takes no more than 1.5 ms. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached. Data Polling: The at89s52 features Data Polling to indicate the end of a write cycle. During a write cycle, an attempted read of the last byte written will result in the complement of the written datum on PO.7. Once the write cycle has been completed, true data are valid on all outputs, and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate BUSY. P3.4 is pulled high again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed, the
programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled.
Chip Erase: The entire Flash Programmable and Erasable Read Only Memory array is erased electrically by using the proper combination of control signals and by holding ALE/PROG low for 10 ms. The code array is written with all “1”s. The chip erase operation must be executed before the code memory can be re-programmed.
Reading the Signature Bytes: The signature bytes are read by the same
procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows.
(030H) = 1EH indicates manufactured by Atmel (031H) = 51H indicates 89C51
(032H) = FFH indicates 12V programming (032H) = 05H indicates 5V programming Programming Interface
Every code byte in the Flash array can be written and the entire array can be erased by using the appropriate combination of control signals. The write operation cycle is selftimed and once initiated, will automatically time itself to completion.
中文翻译
描述
at89s52是美国ATMEL公司生产的低电压，高性能CMOS8位单片机，片内含4Kbytes的快速可擦写的只读程序存储器（PEROM）和128 bytes 的随机存取数据存储器（RAM），器件采用ATMEL公司的高密度、非易失性存储技术生产，兼容标准MCS-51产品指令系统，片内置通用8位中央处理器（CPU）和flish存储单元，功能强大at89s52单片机可为您提供许多高性价比的应用场合，可灵活应用于各种控制领域。
主要性能参数：
与MCS-51产品指令系统完全兼容 4K字节可重复写flash闪速存储器 1000次擦写周期 全静态操作：0HZ－24MHZ 三级加密程序存储器 128*8字节内部RAM 32个可编程I/O口 2个16位定时／计数器 6个中断源
可编程串行UART通道 低功耗空闲和掉电模式 功能特性概述
AT89S52提供以下标准功能：4K 字节flish闪速存储器，128字节内部RAM，32个I/O口线，两个16位定时／计数器，一个5向量两级中断结构，一个全双工串行通信口，片内振荡器及时钟电路。同时，at89s52可降至0HZ的静态逻辑操作，并支持两种软件可选的节电工作模式。空闲方式停止CPU的工作，但允许RAM，定时／计数器，串行通信口及中断系统继续工作。掉电方式保存RAM中的内容，但振荡器停止工作并禁止其它所有部件工作直到下一个硬件复位。
方框图
引脚功能说明 Vcc：电源电压 GND：地
P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复位口。
作为输出口用时，每位能吸收电流的方式驱动8个逻辑门电路，对端口写“1”可 作为高阻抗输入端用。 在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8位）和数据总线复用，在访问期间激活内部上拉电阻。 P1口：P1是一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可做熟出口。做输出口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（Iil）. Flash编程和程序校验期间，P1接受低8位地址。 P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部地山拉电阻把端口拉到高电平，此时可作为输出口，作输出口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流（Iil）。 在访问外部程序存储器获16位地址的外部数据存储器（例如执行 MOVX @DPTR指令）时，P2口送出高8位地址数据。在访问8位地址的外部数据存储器（如执行 MOVX @RI指令）时，P2口线上的内容（也即特殊功能寄存器（SFR）区中R2寄存器的内容），在整个访问期间不改变。 Flash编程或校验时，P2亦接受高地址和其它控制信号。 P3口：P3口是一组带有内部上拉电阻的8位双向I/O口。P3口输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对P3口写入“1”时，他们被内部上拉电阻拉高并可作为输出口。做输出端时，被外部拉低的P3口将用上拉电阻输出电流（Iil）。P3口除了作为一般的I/O口线外，更重要的用途是它的第二功能，如下表所示： 端口引脚 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 rxd (串行输入口) txd (串行输出口) ^int0 (外中断0) ^int1 (外中断1) t0 (定时/计数器0) t1 (定时/计数器1) ^WR (外部数据存储器写选通) ^RD (外部数据存储器读选通) 第二功能 P3口还接收一些用于flash闪速存储器编程和程序校验的控制信号。 RST：复位输入。当振荡器工作时，RST引脚出现两
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