2013级集成电路EDA设计与实践
--f_funcc.vhd--实现了异或、s盒和p置换
--***************
library ieee;
use ieee.std_logic_1164.all; entity f_funcc is
port(r:in std_logic_vector(1 to 32); k:in std_logic_vector(1 to 48); fout:out std_logic_vector(1 to 32)); end f_funcc;
architecture mix of f_funcc is
signal a_s,c_s:std_logic_vector(1 to 48); signal b_s:std_logic_vector(1 to 32); component sboxc
port(a:in std_logic_vector(1 to 48); couta:out std_logic_vector(1 to 32)); end component; begin process(r,k)
variable a_v:std_logic_vector(1 to 48); begin
a_v(1 to 6):=r(32)&r(1 to 5); a_v(7 to 12):=r(4 to 9); a_v(13 to 18):=r(8 to 13); a_v(19 to 24):=r(12 to 17); a_v(25 to 30):=r(16 to 21); a_v(31 to 36):=r(20 to 25); a_v(37 to 42):=r(24 to 29); a_v(43 to 48):=r(28 to 32)&r(1); a_s<=a_v xor k; end process;
u:sboxc port map(a_s,b_s); process(b_s)
variable b_v:std_logic_vector(1 to 32); begin
b_v(1 to 4):=b_s(16)&b_s(7)&b_s(20)&b_s(21); b_v(5 to 8):=b_s(29)&b_s(12)&b_s(28)&b_s(17); b_v(9 to 12):=b_s(1)&b_s(15)&b_s(23)&b_s(26); b_v(13 to 16):=b_s(5)&b_s(18)&b_s(31)&b_s(10); b_v(17 to 20):=b_s(2)&b_s(8)&b_s(24)&b_s(14); b_v(21 to 24):=b_s(32)&b_s(27)&b_s(3)&b_s(9); b_v(25 to 28):=b_s(19)&b_s(13)&b_s(30)&b_s(6); b_v(29 to 32):=b_s(22)&b_s(11)&b_s(4)&b_s(25);
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2013级集成电路EDA设计与实践
fout<=b_v; end process; end mix;
--*************************************************************
--encryc.vhd--l/r交叉输出
--**********
library ieee;
use ieee.std_logic_1164.all; entity encryc is
port(lin:in std_logic_vector(1 to 32); rin:in std_logic_vector(1 to 32); subkey:in std_logic_vector(1 to 48); lout:out std_logic_vector(1 to 32); rout:out std_logic_vector(1 to 32)); end encryc;
architecture mix of encryc is
signal f_s:std_logic_vector(1 to 32); component f_funcc
port(r:in std_logic_vector(1 to 32); k:in std_logic_vector(1 to 48); fout:out std_logic_vector(1 to 32)); end component; begin
u1:f_funcc port map(rin,subkey,f_s); rout<=Lin xor f_s; lout<=rin; end;
--********************************************************
--des.vhd--16轮盒
--***********
LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; entity des is
port( zmingwen:in std_logic_vector(1 to 64);-- mingwen
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