数字逻辑与数字系统课程设计简单计算器

q1<=\when\

…………………………….

3、四选一数据选择器模块

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity mux4_1 is port( d0,d1,d2,d3 :in std_logic_vector(3 downto 0); q :out std_logic_vector(3 downto 0); sel :in std_logic_vector(1 downto 0) ); end mux4_1;

architecture rtl of mux4_1 is begin

process(sel)

begin ------实现从四个数据中选择一个出来

if(sel = \

q<=d0; elsif(sel = \ q<=d1; elsif(sel = \ q<=d2; elsif(sel = \ q<=d3; end if; end process; end rtl;

4、七段显示译码器模块

library ieee;

use ieee.std_logic_1164.all; entity bcd_7dis is

port (bcdm: in std_logic_vector(3 downto 0); a,b,c,d,e,f,g : out std_logic); end bcd_7dis;

architecture art of bcd_7dis is

signal w : std_logic_vector(6 downto 0); begin

process(bcdm) begin

a<=w(6);b<=w(5);c<=w(4);d<=w(3);e<=w(2);f<=w(1);g<=w(0); case bcdm is -----实现8421码转化为2进制码的转换 when \

when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when others =>w<=\ end case; end process; end art;

5、模4计数器模块

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity mo4 is port( q :out std_logic_vector(1 downto 0); clk :in std_logic); end mo4;

architecture rtl of mo4 is

signal qcl : std_logic_vector(1 downto 0); begin process(clk)

begin ----实现模为4的计数

if(clk'event and clk = '1')then if(qcl = \ qcl <= \ else qcl <= qcl + '1'; end if; end if; q <= qcl; end process;

end rtl;

6、模8计数器块

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity count_8 is port( clk:in std_logic;

ql :out std_logic_vector(2 downto 0)); end count_8;

architecture rt1 of count_8 is

signal qcl:std_logic_vector(2 downto 0); begin

process(clk) begin

---- 实现模8的计数

if(clk'event and clk='1') then if (qcl=\ qcl<=\ else

qcl<=qcl+'1'; end if; end if; ql<=qcl; end process; end rt1;

7、3—8译码器块

library ieee;

use ieee.std_logic_1164.all; entity decode3_8 is

port(d :in std_logic_vector(2 downto 0);

y :out std_logic_vector(7 downto 0)); end decode3_8 ;

architecture rt1 of decode3_8 is begin process(d) begin

case d is

------实现3对8的译码

when \when \when \when \when others=>y<=\end case; end process; end rt1;

六、各模块仿真结果 1、计算器模块

2、八位二进制数转化成8421BCD码模块

3.、四选一数据选择器模块

4、七段显示译码器模块