程控交换铃流信号课程设计

end rtl256;

library ieee; ——1秒通4秒断的脉冲信号 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity entity5 is port(clk:in std_logic; clk_div5:out std_logic); end entity5;

architecture rtl5 of entity5 is

signal count:std_logic_vector(2 downto 0):=\begin

process(clk) begin

if(clk'event and clk='1') then

if(count=\ count<=\ else

count<=count+1; end if; end if; end process; process(clk) begin

if(clk'event and clk='1') then if(count=\ clk_div5<='1'; else

clk_div5<='0'; end if; end if; end process; end rtl5;

library ieee; --20分频得到25Hz的方波 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity entity20 is port(clk:in std_logic; clk_div20:out std_logic); end entity20;

architecture rtl20 of entity20 is signal clk_temp:std_logic:='0';

signal count:std_logic_vector(3 downto 0):=\begin

process(clk) begin

if(clk'event and clk='1') then if(count=\

clk_temp<=not clk_temp; count<=\ else count<=count+1; end if; end if; end process;

clk_div20<=clk_temp; end rtl20;

library ieee; ——最后的链接文件 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jh is port(

clk:in std_logic;

clk1:out std_logic;--拨号音 clk2:out std_logic;--回铃音 clk3:out std_logic;--忙音 clk4:out std_logic);--振铃音 end entity;

architecture art of jh is

signal clk1hz,clk02hz,clk25:std_logic:='0'; component entity450 is port(clk:in std_logic;

clk_div450:out std_logic); end component; component entity5 is port(clk:in std_logic; clk_div5:out std_logic); end component;

component entity20 is port(clk:in std_logic; clk_div20:out std_logic); end component; begin

u0:entity450 port map(clk,clk1hz); u1:entity5 port map(clk1hz,clk02hz); u2:entity20 port map(clk,clk25);

clk1<=clk;

clk2<=clk and clk02hz; clk3<=clk and clk1hz; clk4<=clk25 and clk02hz; end;

3.2 QuartusII软件仿真运行结果

（1）、拨号音：连续发送的450Hz信号

（2）、回铃音：1秒通，4秒断的5秒断续的450Hz信号。

（3）、忙音：0.5秒通，0.5秒断的1秒断续的450Hz信号

（4）、振铃信号(铃流)：频率为25Hz，以1秒通，4秒断的5秒断续方式发送

波形展开前的波形