TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005INPUT AND OUTPUT CLOCKS (CONTINUED)
ECLKIN
15ECLKOUT1
62344Figure 20. ECLKOUT1 Timing for EMIFA and EMIFB Modules
switching characteristics over recommended operating conditions for ECLKOUT2 for the EMIFAand EMIFB modules??§ (see Figure 21)
NO.
PARAMETER
?5E0, A?5E0,?6E3, A?6E3,
?7E3MIN
123456
??
UNIT
MAX±175?
tJ(EKO2)tw(EKO2H)tw(EKO2L)tt(EKO2)td(EKIH-EKO2H)td(EKIH-EKO2L)
Period jitter, ECLKOUT2Pulse duration, ECLKOUT2 highPulse duration, ECLKOUT2 lowTransition time, ECLKOUT2
Delay time, ECLKIN high to ECLKOUT2 highDelay time, ECLKIN high to ECLKOUT2 low
11
0
0.5NE ? 0.70.5NE ? 0.7
psnsnsnsnsns
0.5NE + 0.70.5NE + 0.7
188
The reference points for the rise and fall transitions are measured at VOL MAX and VOH MIN.
These C64x? devices have two EMIFs (64-bit EMIFA and 16-bit EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals areprefixed by a “B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted.§E = the EMIF input clock (ECLKIN, CPU/4 clock, or CPU/6 clock) period in ns for EMIFA or EMIFB.N = the EMIF input clock divider; N = 1, 2, or 4.
?This cycle-to-cycle jitter specification was measured with CPU/4 or CPU/6 as the source of the EMIF input clock.
5ECLKIN
163244ECLKOUT2
Figure 21. ECLKOUT2 Timing for the EMIFA and EMIFB Modules
TMS320C6414, TMS320C6415, TMS320C6416FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS146N ? FEBRUARY 2001 ? REVISED MAY 2005ASYNCHRONOUS MEMORY TIMING
timing requirements for asynchronous memory cycles for EMIFA module??§(see Figure 22 and Figure 23)
NO.
?5E0?6E3?7E3MIN
3467
?
A?5E0A?6E3MIN6.5131.51.5
MAX
UNIT
MAX
tsu(EDV-AREH)th(AREH-EDV)tsu(ARDY-EKO1H)th(EKO1H-ARDY)
Setup time, EDx valid before ARE highHold time, EDx valid after ARE highSetup time, ARDY valid before ECLKOUTx highHold time, ARDY valid after ECLKOUTx high
Rev 1.1 andearlierRev 2.0
6.51311.3
nsnsnsnsns
To ensure data setup time, simply program the strobe width wide enough. ARDY is internally synchronized. The ARDY signal is only recognizedtwo cycles before the end of the programmed strobe time and while ARDY is low, the strobe time is extended cycle-by-cycle. When ARDY isrecognized low, the end of the strobe time is two cycles after ARDY is recognized high. To use ARDY as an asynchronous input, the pulse widthof the ARDY signal should be wide enough (e.g., pulse width = 2E) to ensure setup and hold time is met.
?RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters areprogrammed via the EMIF CE space control registers.
§These C64x? devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronousmemory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, andBAWE (for EMIFB)].switching characteristics over recommended operating conditions for asynchronous memorycycles for EMIFA module?§?# (see Figure 22 and Figure 23)
NO.
PARAMETER
?5E0, A?5E0,?6E3, A?6E3,
?7E3
MIN
1258910
?UNIT
MAX
nsns7
nsnsns
7.1
ns
tosu(SELV-AREL)toh(AREH-SELIV)td(EKO1H-AREV)tosu(SELV-AWEL)toh(AWEH-SELIV)td(EKO1H-AWEV)
Output setup time, select signals valid to ARE lowOutput hold time, ARE high to select signals invalidDelay time, ECLKOUTx high to ARE validOutput setup time, select signals valid to AWE lowOutput hold time, AWE high to select signals invalidDelay time, ECLKOUTx high to AWE validRS * E ? 1.5RH * E ? 1.9
1
WS * E ? 1.7WH * E ? 1.8
1.3
RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold. These parameters areprogrammed via the EMIF CE space control registers.
§These C64x? devices have two EMIFs (EMIFA and EMIFB). All EMIFA signals are prefixed by an “A” and all EMIFB signals are prefixed by a“B”. Throughout the rest of this document, in generic EMIF areas of discussion, the prefix “A” or “B” may be omitted [e.g., the asynchronousmemory access signals are shown as generic (AOE, ARE, and AWE) instead of AAOE, AARE, and AAWE (for EMIFA) and BAOE, BARE, andBAWE (for EMIFB)].?E = ECLKOUT1 period in ns for EMIFA or EMIFB
#Select signals for EMIFA include: ACEx, ABE[7:0], AEA[22:3], AAOE; and for EMIFA writes, include AED[63:0].Select signals EMIFB include: BCEx, BBE[1:0], BEA[20:1], BAOE; and for EMIFB writes, include BED[15:0].
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