Chapter 5:Configuration Details
Each logical bit of the FUSE_KEY and FUSE_CNTL registers consists of two eFUSE cells (primary and redundant), a flip-flop, and common logic elements for data multiplexing.
eFUSE Registers
A Spartan-6 FPGA has a total of three eFUSE registers. Table5-18 lists the eFUSE registers in Spartan-6 devices with their sizes and usage. The eFUSE bits are addressed so that the LSB is shifted in/out first and MSB is last.
Table 5-18:
eFUSE Registers
Size(Bits)256
[0:255]
(bit 255 shifted first)
Contents
Bitstream encryption key
Description
Stores key for use by AES bitstream decryptor. The eFUSE key can be used instead of the key stored in battery-backed SRAM. The AES key is used by the Spartan-6 FPGA decryption engine to load encrypted bitstreams. Depending on the read/write access bits in the CNTL register, the AES key can be programmed and read through the JTAG port.
Stores device DNA, a read-only register that is accessed through the JTAG port or the DNA_PORT primitive.Controls key use and read/write access to eFUSE registers. This register can be programmed and read through the JTAG port.
Register NameFUSE_KEY(1)
FUSE_ID57Device DNA[0:56]
(bit 56 shifted first)
FUSE_CNTL(1)
32Control BitsCNTL [31:0](bit 0 shifted first)
Notes:
1.FUSE_KEY and FUSE_CNTL are only available on 6SLX75/T, 6SLX100/T, and 6SLX150/T devices.
eFUSE Control Register (FUSE_CNTL)
This register contains six user programmable bits. These bits are used to select AES key usage and set the read/write protection for eFUSE registers, as detailed in Table5-19. Bit 0 is shifted in or out first.
The eFUSE bits are one-time programmable (OTP). Once programmed, they cannot be unprogrammed. For example, if access to a register is disabled, it cannot be re-enabled.Table 5-19:Bit #0:78
eFUSE CNTL Register BitsName--Description
Reserved
The user must program this bit after programming and verifying AES and CNTL registers to prevent any manipulation or readback of these registers.Reserved
Comments
CNTL SecurityDisable read and write of
the CNTL registers. Redundant with CNTL[12].
-Key Security
-
910
Disables read and write of The user must program this bit after KEY register. Redundant programming and verifying AES with CNTL[14].registers to prevent manipulation or
readback of these registers.-Reserved
11-
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Configuration Packets
Suspend Register (PWRDN_REG)
Table 5-37:
FieldRESERVEDEN_EYES
Power-Down Register DescriptionBit Index
1514
Reserved.
Enable Multi-Pin Wake-Up.0: Disable Multi-Pin Wake-Up.1: Enable Multi-Pin Wake-Up.Reserved.
0: Suspend filter (300ns) on.1: Filter off.
0: No GSR pulse during return from Suspend.1: Generate GSR pulse during return from Suspend.Reserved.
0: Suspend is disabled.1: Suspend is enabled.
0: Use MCCLK for startup sequence initiated by power-up.
1: Use SSCLKSRC for startup sequence initiated by power-up.
010
Description
BitGen Default
RESERVEDFILTER_BEN_PGSR
13:654
0010_0010
00
RESERVEDEN_PWRDNKEEP_SCLK
320
Frame Length Register
Frame Length Register (FLR) is written with the length of a frame, as measured in 16-bit words, near the beginning of the configuration bitstream. FLR must be written before any FDR operation will work. It is not necessary to set the FLR more than once.The actual value written to FLR = Actual Frame Length.
Based on the segmentation scheme in Spartan-6 devices, the frame length for type0 (CLB, IOI, and special blocks) and type1 (block RAM) are fixed. The only block that needs a specified frame length is IOB.Table 5-38:
Bits[15:0]
Frame Length Register
FLR
xxxxxxxxxxxxxxxx
Multi-Frame Write Register
The Spartan-6 FPGA supports Multi-Frame Write (MFWR) for first-time configuration but does not support it during reconfiguration. The FPGA has to go through one power cycle or use PROGRAM_B to reset the chip before MFWR can be used.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 6:Readback and Configuration Verification
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
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