VHDL数字逻辑电路设计19例

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6. 例712

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY L712 IS

PORT(CP: IN STD_LOGIC;

F: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY L712;

ARCHITECTURE rt1 OF L712 IS --调用193

COMPONENT JSQ193

PORT(CLR,LOADN,CPU,CPD: IN STD_LOGIC;

DATA: IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); QCCN,QCBN: OUT STD_LOGIC); END COMPONENT JSQ193;

SIGNAL QT:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CLRT,QCCNT,QCBNT:STD_LOGIC;

BEGIN

CLRT<=QT(3) AND QT(1);

U: JSQ193 PORT map(CLRT,'1',CP,'1',\F<=QT;

END ARCHITECTURE rt1;

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7. 例713

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY L713 IS

PORT(CP,LOADNX: IN STD_LOGIC;

F: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY L713;

ARCHITECTURE rt1 OF L713 IS --调用193

COMPONENT JSQ193 IS

PORT(CLR,LOADN,CPU,CPD: IN STD_LOGIC;

DATA: IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); QCCN,QCBN: OUT STD_LOGIC); END COMPONENT JSQ193;

SIGNAL QT:STD_LOGIC_VECTOR(3 DOWNTO 0); SIGNAL CLRT,QCCNT,QCBNT,LOADNT:STD_LOGIC;

BEGIN

LOADNT<=LOADNX AND (QT(3) OR QT(2));

U: JSQ193 PORT map(CLRT,LOADNT,'1',CP,\F<=QT;

END ARCHITECTURE rt1;

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8． 例714

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY L714 IS

PORT(CP: IN STD_LOGIC;

FH,FL: OUT STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY L714;

ARCHITECTURE rt1 OF L714 IS --调用193

COMPONENT JSQ193 IS

PORT(CLR,LOADN,CPU,CPD: IN STD_LOGIC;

DATA: IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); QCCN,QCBN: OUT STD_LOGIC); END COMPONENT JSQ193;

SIGNAL QTH,QTL:STD_LOGIC_VECTOR(3 DOWNTO 0);

SIGNAL CLRT,QCCNTH,QCBNTH,QCCNTL,QCBNTL:STD_LOGIC; BEGIN

CLRT<=QTH(3) AND QTH(0) AND QTL(1) AND QTL(0);

U1: JSQ193 PORT map(CLRT,'1',CP,'1',\

U2: JSQ193 PORT map(CLRT,'1',QCCNTL,'1',\FH<=QTH;FL<=QTL;

END ARCHITECTURE rt1;

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9. 移位寄存器194 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY shft194 IS

PORT( d: IN STD_LOGIC_VECTOR(3 DOWNTO 0); CP,clrn,DL,DR: IN STD_LOGIC;

S: IN STD_LOGIC_VECTOR(1 DOWNTO 0); q: buffer STD_LOGIC_VECTOR(3 DOWNTO 0)); END ENTITY shft194;

ARCHITECTURE rt1 OF shft194 IS

BEGIN

PROCESS(CP,CLRN,DL,DR,S,D)

BEGIN

if clrn ='0' then q<=\

ELSIF(CP='1' AND CP'EVENT) THEN

case S is

when \ when \ when \ when others =>null; end case; end if; END PROCESS ;

END ARCHITECTURE rt1;

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