The connections to the global and regional clocks from the top clock pins and enhanced PLL outputs are shown in Table2–28. The connections to the clocks from the bottom clock pins are shown in Table2–29.
Table2–28.Global and Regional Clock Connections from Top Clock Pins and Enhanced PLL Outputs(Part 1 of2)
Top Side Global and Regional Clock Network
Connectivity
Clock pinsCLK12pCLK13pCLK14pCLK15pCLK12nCLK13nCLK14nCLK15n
Drivers from internal logicGCLKDRV0GCLKDRV1GCLKDRV2GCLKDRV3RCLKDRV0RCLKDRV1RCLKDRV2RCLKDRV3RCLKDRV4RCLKDRV5RCLKDRV6RCLKDRV7
Enhanced PLL5 outputsc0c1
RCLK24RCLK25RCLK26RCLK27RCLK28RCLK29RCLK30vvvv
vvvv
vv
vv
vv
vv
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
vv
vv
vv
v
v
v
v
v
v
v
v
v
v
Stratix II GX Device Handbook, Volume 1
RCLK31DLLCLKCLK12CLK13CLK14CLK15Stratix II GX Architecture
Table2–28.Global and Regional Clock Connections from Top Clock Pins and Enhanced PLL Outputs(Part 2 of2)
Top Side Global and Regional Clock Network
Connectivity
c2c3c4c5
Enhanced PLL 11 outputsc0c1c2c3c4c5
DLLCLKRCLK24RCLK25RCLK26RCLK27RCLK28RCLK29RCLK30vvvvRCLK14vv
vvvv
vv
vv
vv
vv
v
vv
v
v
vv
v
v
v
v
v
v
v
v
v
v
vv
v
vv
vv
vv
vv
Table2–29.Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL Outputs(Part 1 of2)Bottom Side Global and Regional Clock Network
Connectivity
Clock pinsCLK4pCLK5pCLK6pCLK7pCLK4nCLK5nCLK6nCLK7n
Drivers from internal logicGCLKDRV0GCLKDRV1
RCLK10RCLK11RCLK12RCLK13vvvv
vv
vv
vv
vv
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Stratix II GX Device Handbook, Volume 1
RCLK15DLLCLKRCLK8RCLK9CLK4CLK5CLK6CLK7RCLK31CLK12CLK13CLK14CLK15PLLs and Clock Networks
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
Enhanced PLLs
Stratix II GX devices contain up to four enhanced PLLs with advanced clock management features. These features include support for external clock feedback mode, spread-spectrum clocking, and counter cascading. Figure2–74 shows a diagram of the enhanced PLL.
Figure2–74.Stratix II GX Enhanced PLL
Note(1)
VCO Phase SelectionSelectable at EachPLL Output PortFrom Adjacent PLLPost-ScaleCountersClockSwitchoverCircuitryINCLK[3..0]4/nPhase FrequencyDetectorSpreadSpectrum/c0/c14PFDChargePumpLoopFilterVCO8/c26/c36/m/c4I/O Buffers (3)8RegionalClocksGlobalClocksGlobal or RegionalClock(2)/c5FBINLock Detect& Filterto I/O or generalroutingShaded Portions of thePLL are ReconfigurableVCO Phase SelectionAffecting All OutputsNotes to Figure2–74:(1)(2)(3)(4)
Each clock source can come from any of the four clock pins that are physically located on the same side of the deviceas the PLL.
If the feedback input is used, you will lose one (or two, if FBIN is differential) external clock output pin.Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
Fast PLLs
Stratix II GX devices contain up to four fast PLLs with high-speed serial interfacing ability. The fast PLLs offer high-speed outputs to manage the high-speed differential I/O interfaces. Figure2–75 shows a diagram of the fast PLL.
Stratix II GX Device Handbook, Volume 1
I/O Structure
Figure2–75.Stratix II GX Device Fast PLL
VCO Phase SelectionSelectable at each PLLOutput PortPost-ScaleCountersGlobal orregional clock (1)ClockSwitchoverCircuitry (4)PhaseFrequencyDetectordiffioclk0(2)÷c0ChargePumpLoopFilter8load_en0(3)ClockInput4÷nPFDVCO÷k÷c14÷c2load_en1(3)diffioclk1(2)Global clocksGlobal orregional clock (1)4÷c3÷m8Regional clocks8to DPA blockShaded Portions of thePLL are ReconfigurableNotes to Figure2–75:(1)
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.In high-speed differential I/O support mode, this high-speed PLL clock feeds the serializer/deserializer (SERDES)circuitry. Stratix II GX devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a differential I/O SERDES control signal.
Stratix II GX fast PLLs only support manual clock switchover.
(2)
(3)(4)
f
Refer to the PLLs in Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device Handbook for more information on enhanced and fast PLLs. Refer to “High-Speed Differential I/O with DPA Support” on page2–136 for more information on high-speed differential I/O support.
The Stratix II GX IOEs provide many features, including:
■■■■■■■■■■■■
I/O Structure
Dedicated differential and single-ended I/O buffers3.3-V, 64-bit, 66-MHz PCI compliance
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
Joint Test Action Group (JTAG) boundary-scan test (BST) supportOn-chip driver series termination
On-chip termination for differential standardsProgrammable pull-up during configurationOutput drive strength controlTri-state buffersBus-hold circuitry
Programmable pull-up resistors
Programmable input and output delays
Stratix II GX Device Handbook, Volume 1
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