Shift registers are useful in DSP functions such as FIR filters. When implementing 18×18 or smaller width multipliers, you do not need external logic to create the shift register chain because the input shift registers are internal to the DSP block. This implementation significantly reduces the logical element (LE) resources required, avoids routing congestion, and results in predictable timing.
The first multiplier in every half DSP block (top- and bottom-half) in StratixIII
devices has a multiplexer for the first multiplier B-input (lower-leg input) register to select between general routing and loopback, as shown in Figure5–6. In loopback mode, the most significant 18-bit registered outputs are connected as feedback to the multiplier input of the first top multiplier in each half DSP block. Loopback modes are used by recursive filters where the previous output is needed to compute the current output.
The loopback mode is described in detail in “Two-Multiplier Adder Sum Mode” on page5–21.
Table5–3 lists the input register modes for the DSP block.
Table5–3.Input Register Modes Register Input Mode (1)Parallel inputShift register input (2)Loopback input (3)Notes to Table5–3:
9×9v——12×12v——18×18vvv36×36v——Doublev——Multiplier and First-Stage Adder
The multiplier stage natively supports 9×9, 12×12, 18×18, or 36×36 multipliers. Other wordlengths are padded up to the nearest appropriate native wordlength; for example, 16×16 would be padded up to use 18×18. Refer to “Independent
Multiplier Modes” on page5–15 for more details. Depending on the data width of the multiplier, a single DSP block can perform many multiplications in parallel.
Each multiplier operand can be a unique signed or unsigned number. Two dynamic signals, signa and signb, control the representation of each operand, respectively. A logic1 value on the signa/signb signal indicates that data A/data B is a signed number; a logic0 value indicates an unsigned number. Table5–4 lists the sign of the multiplication result for the various operand sign representations. The result of the multiplication is signed if any one of the operands is a signed value.
Table5–4.Multiplier Sign Representation
Data A (signa Value)Unsigned (logic0)Unsigned (logic0)Signed (logic1)Signed (logic1)Stratix III Device Handbook, Volume 1
Data B (signb Value)Unsigned (logic0)Signed (logic1)Unsigned (logic0)Signed (logic1)ResultUnsignedSignedSignedSignedChapter 5:DSP Blocks in StratixIII DevicesDSP Block Resource Descriptions
Each Half Block has its own signa and signb signal. Therefore, all of the dataA inputs feeding the same DSP Half Block must have the same sign representation. Similarly, all of the dataB inputs feeding the same DSP Half Block must have the same sign representation. The multiplier offers full precision regardless of the sign representation in all operational modes except for full precision 18x18 loopback and Two-Multiplier Adder modes. Refer to “Two-Multiplier Adder Sum Mode” on page5–21 for details.1
When the signa and signb signals are unused, the QuartusII software sets the multiplier to perform unsigned multiplication by default.
The outputs of the multipliers are the only outputs that can feed into the first-stage adder, as shown in Figure5–6. There are four first-stage adders in a DSP block (two adders per half DSP block). The first-stage adder block has the ability to perform addition and subtraction. The control signal for addition or subtraction is static and has to be configured upon compile time. The first-stage adders are used by the sum modes to compute the sum of two multipliers, 18×18-complex multipliers, and to perform the first stage of a 36×36 multiply and shift operation.
Depending on your specifications, the output of the first-stage adder has the option to feed into the pipeline registers, second-stage adder, round and saturation unit, or the output registers.
Pipeline Register Stage
The output from the first-stage adder can either feed or bypass the pipeline registers, as shown in Figure5–6. Pipeline registers increase the DSP block’s maximum performance (at the expense of extra cycles of latency), especially when using the subsequent DSP block stages. Pipeline registers split up the long signal path between the input-registers/multiplier/first-stage adder and the second-stage
adder/round-and-saturation/output-registers, creating two shorter paths.
Second-Stage Adder
There are four individual 44-bit second-stage adders per DSP block (2adders per half DSP block). You can configure the second-stage adders as follows:
■■■■
The final stage of a 36-bit multiplierA sum of four (18×18)
An accumulator (44-bits maximum)
A chained output summation (44-bits maximum)
111
The chained-output adder can be used at the same time as a second-level adder in chained output summation mode.
The output of the second-stage adder has the option to go into the round and saturation logic unit or the output register.
You cannot use the second-stage adder independently from the multiplier and first-stage adder.
Stratix III Device Handbook, Volume 1
Chapter 5:DSP Blocks in StratixIII Devices
DSP Block Resource Descriptions
Stratix III Device Handbook, Volume 1
Chapter 5:DSP Blocks in StratixIII DevicesOperational Mode Descriptions
The second-stage and output registers are triggered by the positive edge of the clock signal and are cleared on power up. The following DSP block signals control the output registers within the DSP block:
■■■
clock[3..0]ena[3..0]aclr[3..0]
Operational Mode Descriptions
The various modes of operation are discussed below.
Independent Multiplier Modes
In independent input and output multiplier mode, the DSP block performs individual multiplication operations for general-purpose multipliers.
9-, 12-, and 18-Bit Multiplier
You can configure each DSP block multiplier for 9-, 12-, or 18-bit multiplication. A single DSP block can support up to eight individual 9×9 multipliers, six 12×12 multipliers, or up to four individual 18×18 multipliers. For operand widths up to 9bits, a 9×9 multiplier is implemented. For operand widths from 10 to 12 bits, a 12×12 multiplier is implemented, and for operand widths from 13 to 18 bits, an 18×18 multiplier is implemented. This is done by the QuartusII software by
zero-padding the LSBs. Figure5–8, Figure5–9, and Figure5–10 show the DSP block in the independent multiplier operation mode.
Figure5–8.18-Bit Independent Multiplier Mode for Half-DSP Block
signaclock[3..0]ena[3..0]aclr[3..0]signboutput_roundoutput_saturateoverflow
dataa_0[17..0]Round/Saturate1836result_0[ ]
Pipeline Register Bankdatab_0[17..0]dataa_1[17..0]1818Round/SaturateOutput Register BankInput Register Bank36result_1[ ]datab_1[17..0]18Half-DSP BlockStratix III Device Handbook, Volume 1
Chapter 5:DSP Blocks in StratixIII DevicesOperational Mode Descriptions
Four-Multiplier Adder
In the four-multiplier adder configuration shown in Figure5–17, the DSP block can implement two four-multiplier adders (one four-multiplier adder per half DSP block). These modes are useful for implementing one-dimensional and two-dimensional filtering applications. The four-multiplier adder is performed in two addition stages. The outputs of two of the four multipliers are initially summed in the two first-stage adder blocks. The results of these two adder blocks are then summed in the
second-stage adder block to produce the final four-multiplier adder result, as shown by Equation5–2 and Equation5–3.
Stratix III Device Handbook, Volume 1
相关推荐：
loading