Defense-grade Zynq-7000QSoC
Data Sheet: Overview
DS196 (v1.3.1) July 2, 2015
Product Specification
Defense-grade Zynq-7000Q SoC First Generation Architecture
The Defense-grade Zynq?-7000Q family is based on the Xilinx SoC architecture. These products integrate a feature-rich dual-core ARM? Cortex?-A9 based processing system (PS) and 28nm Xilinx programmable logic (PL) in a single device for extreme environment applications such as Aerospace and Defense. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces.
Processing System (PS)
Defense-grade Zynq-7000Q Features
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Full-range extended temperature testingMask set control
Fully leaded (Pb) content
Ruggedized packaging (RB, RF)Long-term availability
Anti-counterfeiting features
Fourth-generation information assurance and anti-tamper support
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1GB of address space using single rank of 8-, 16-, or 32-bit-widememories
Static memory interfaces?8-bit SRAM data bus with up to 64MB support?Parallel NOR flash support?ONFI1.0 NAND flash support (1-bit ECC)?
1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), or two quad-SPI (8-bit)
serial NOR flash
Dual-core ARM? Cortex?-A9 Based Application Processor Unit (APU)
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2.5 DMIPS/MHz per CPU
CPU frequency: Up to 800MHzCoherent multiprocessor supportARMv7-A architecture?TrustZone? security?Thumb?-2 instruction set
Jazelle? RCT execution Environment ArchitectureNEON? media-processing engine
Single and double precision Vector Floating Point Unit (VFPU)CoreSight? and Program Trace Macrocell (PTM)Timer and Interrupts?Three watchdog timers?One global timer?Two triple-timer counters
8-Channel DMA Controller
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Memory-to-memory, memory-to-peripheral, peripheral-to-memory,
and scatter-gather transaction support
I/O Peripherals and Interfaces
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Two 10/100/1000 tri-speed Ethernet MAC peripherals withIEEEStd802.3 and IEEEStd1588 revision 2.0 support?Scatter-gather DMA capability?Recognition of 1588 rev. 2 PTP frames?GMII, RGMII, and SGMII interfaces
Two USB 2.0 OTG peripherals, each supporting up to 12 Endpoints?USB 2.0 compliant device IP core?Supports on-the-go, high-speed, full-speed, and low-speed
modes
Intel EHCI compliant USB host??8-bit ULPI external PHY interfaceTwo full CAN 2.0B compliant CAN bus interfaces?CAN 2.0-A and CAN 2.0-B and ISO 118981-1 standard
compliant
External PHY interface?
Two SD/SDIO 2.0/MMC3.31 compliant controllers
Two full-duplex SPI ports with three peripheral chip selectsTwo high-speed UARTs (up to 1Mb/s)Two master and slave I2C interfaces
GPIO with four 32-bit banks, of which 54 bits can be used with the PS I/O (one bank of 32b and one bank of 22b) and up to 64 bits (up totwo banks of 32b) connected to the Programmable Logic
54 flexible multiplexed I/O (MIO) for peripheral pin assignments
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Caches
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32KB Level1 4-way set-associative instruction and data caches(independent for each CPU)
512KB 8-way set-associative Level2 cache(shared between the CPUs)Byte-parity support
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On-Chip Memory
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On-chip boot ROM
256KB on-chip RAM (OCM)Byte-parity support
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External Memory Interfaces
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Multiprotocol dynamic memory controller
16-bit or 32-bit interfaces to DDR3, DDR3L, DDR2, or LPDDR2memories
ECC support in 16-bit mode
Interconnect
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High-bandwidth connectivity within PS and between PS and PLARM AMBA? AXI based
QoS support on critical masters for latency and bandwidth control
DS196 (v1.3.1) July 2, 2015Product Specification
Data Sheet: Overview
DS196 (v1.3.1) July 2, 2015Product Specification
Data Sheet: Overview
Processor System Description
As shown in Figure1, the PS comprises four major blocks:????
Application processor unit (APU)Memory interfacesI/O peripherals (IOP)Interconnect
Figure1 illustrates the functional blocks of the Zynq-7000 SoC. For more information on the functional blocks, see UG585, Zynq-7000 SoC Technical Reference Manual.
X-Ref Target - Figure 1Zynq-7000 SoCI/OPeripherals USBUSBGigEGigESDSDIOSDSDIOGPIOUARTUARTCANCANI2CI2CSPISPIMemoryInterfaces SRAM/NOR ONFI 1.0NAND Q-SPICTRL Processing SystemClockGeneration2x USB2x GigE2x SDIRQResetSWDTTTCSystem-LevelControlRegsDMA 8ChannelOCM InterconnectCentralInterconnectCoreSight ComponentsDAPDevCProgrammable Logic to Memory InterconnectMMU32 KBI-CacheGICApplication Processor UnitFPU and NEON EngineARM Cortex-A9CPU32 KBD-CacheFPU and NEON EngineMMU32 KBI-CacheARM Cortex-A9CPU32 KBD-CacheSnoop Controller, AWDT, Timer512 KB L2 Cache & ControllerMIO256K SRAMMemoryInterfaces DDR2/3, DDR3L,LPDDR2Controller EMIOXADC12-Bit ADCGeneral-PurposePortsDMASync IRQConfigAES/SHAHigh-Performance PortsACPProgrammable LogicSelectIOResourcesNotes:1)Arrow direction shows control (master to slave)2)Data flows in both directions: AXI 32-Bit/64-Bit, AXI 64-Bit, AXI 32-Bit, AHB 32-Bit, APB 32-Bit, CustomDS196_01_070318Figure 1:Zynq-7000 SoC OverviewDS196 (v1.3.1) July 2, 2015Product Specification
Data Sheet: Overview
DS196 (v1.3.1) July 2, 2015Product Specification
Data Sheet: Overview
Zynq DeviceXQ7Z020XQ7Z030XQ7Z045XQ7Z100
MMCM4588
PLL4588
Mixed-Mode Clock Manager and Phase-Locked Loop
The MMCM and PLL share many characteristics. Both can serve as a frequency synthesizer for a wide range of frequencies and as a jitter filter for incoming clocks. At the center of both components is a voltage-controlled oscillator (VCO), which speeds up and slows down depending on the input voltage it receives from the phase frequency detector (PFD).
There are three sets of programmable frequency dividers: D, M, and O. The pre-divider D (programmable by configuration and afterwards via DRP) reduces the input frequency and feeds one input of the traditional PLL phase/frequency
comparator. The feedback divider M (programmable by configuration and afterwards via DRP) acts as a multiplier because it divides the VCO output frequency before feeding the other input of the phase comparator. D and M must be chosen appropriately to keep the VCO within its specified frequency range. The VCO has eight equally-spaced output phases (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to drive one of the output dividers (six for the PLL, O0 to O5, and seven for the MMCM, O0 to O6), each programmable by configuration to divide by any integer from 1 to 128.The MMCM and PLL have three input-jitter filter options: Low-bandwidth mode, which has the best jitter attenuation;
high-bandwidth mode, which has the best phase offset; and optimized mode, which allows the tools to find the best setting.
DS196 (v1.3.1) July 2, 2015Product Specification
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