FPGA可编程逻辑器件芯片EP1S40F780I6N中文规格书 - 图文

Stratix II GX Architecture

Figure2–60.DSP Block Interface to Interconnect

C4 InterconnectDirect Link Interconnectfrom Adjacent LABR4 InterconnectDirect Link Outputsto Adjacent LABsDirect Link Interconnectfrom Adjacent LAB36DSP BlockRow StructureLAB1836LAB16161236ControlA[17..0]B[17..0]OA[17..0]OB[17..0]36Row InterfaceBlockDSP Block toLAB Row InterfaceBlock Interconnect Region36 Inputs per Row36 Outputs per RowA bus of 44 control signals feeds the entire DSP block. These signals include clocks, asynchronous clears, clock enables, signed and unsigned control signals, addition and subtraction control signals, rounding and saturation control signals, and accumulator synchronous loads. The clock signals are routed from LAB row clocks and are generated from specific LAB rows at the DSP block interface. The LAB row source for control signals, data inputs, and outputs is shown in Table2–23.

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Refer to the DSP Blocks in Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device Handbook for more information on DSP blocks.

Stratix II GX Device Handbook, Volume 1