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FPGA可编程逻辑器件芯片AD603ARZ-REEL中文规格书 - 图文

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Data Sheet

FEATURES

Linear-in-dB gain control

Pin-programmable gain ranges

?11 dB to +31 dB with 90 MHz bandwidth 9 dB to 51 dB with 9 MHz bandwidth

Any intermediate range, for example ?1 dB to +41 dB with 30 MHz bandwidth

Bandwidth independent of variable gain 1.3 nV/√Hz input noise spectral density ±0.5 dB typical gain accuracy

AD603

The decibel gain is linear in dB, accurately calibrated, and stable over temperature and supply. The gain is controlled at a high impedance (50 MΩ), low bias (200 nA) differential input; the scaling is 25 mV/dB, requiring a gain control voltage of only 1 V to span the central 40 dB of the gain range. An overrange and underrange of 1 dB is provided whatever the selected range. The gain control response time is less than 1 μs for a 40 dB change. The differential gain control interface allows the use of either differential or single-ended positive or negative control voltages. Several of these amplifiers may be cascaded and their gain control gains offset to optimize the system SNR.

The AD603 can drive a load impedance as low as 100 Ω with low distortion. For a 500 Ω load in shunt with 5 pF, the total harmonic distortion for a ±1 V sinusoidal output at 10 MHz is typically ?60 dBc. The peak specified output is ±2.5 V minimum into a 500 Ω load.

The AD603 uses a patented proprietary circuit topology—the X-AMP?. The X-AMP comprises a variable attenuator of 0 dBto ?42.14 dB followed by a fixed-gain amplifier. Because of theattenuator, the amplifier never has to cope with large inputs andcan use negative feedback to define its (fixed) gain and dynamicperformance. The attenuator has an input resistance of 100 Ω,laser trimmed to ±3%, and comprises a 7-stage R-2R laddernetwork, resulting in an attenuation between tap points of6.021 dB. A proprietary interpolation technique provides acontinuous gain control function that is linear in dB.The AD603 is specified for operation from ?40°C to +85°C.

APPLICATIONS

RF/IF AGC amplifiers Video gain controls A/D range extensions Signal measurements

GENERAL DESCRIPTION

The AD603 is a low noise, voltage-controlled amplifier for use in RF and IF AGC systems. It provides accurate, pin-selectable gains of ?11 dB to +31 dB with a bandwidth of 90 MHz or +9 dB to 51+ dB with a bandwidth of 9 MHz. Any intermediate gain range may be arranged using one external resistor. The input referred noise spectral density is only 1.3 nV/√Hz, and power consumption is 125 mW at the recommended ±5 V supplies.

FUNCTIONAL BLOCK DIAGRAM

SCALINGREFERENCEGPOSVGGNEGGAIN-CONTROLINTERFACEPRECISIONPASSIVEINPUTATTENUATORFIXED-GAINAMPLIFIERVOUTAD6036.44k?*FDBK694?*0dBVINPR–6.02dBR–12.04dB–18.06dB–24.08dBRRR–30.1dBR–36.12dB–42.14dBR20?*2R2R2R2R2R2RRCOMMR-2R LADDER NETWORK*NOMINALVALUES.00539-001Figure 1.

Rev. K

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD603

THEORY OF OPERATION

The AD603 comprises a fixed-gain amplifier, preceded by a broadband passive attenuator of 0 dB to 42.14 dB, having a gain control scaling factor of 40 dB per volt. The fixed gain is laser-trimmed in two ranges, to either 31.07 dB (×35.8) or 50 dB (×358), or it may be set to any range in between using one external resistor between Pin 5 and Pin 7. Somewhat higher gain can be obtained by connecting the resistor from Pin 5 to common, but the increase in output offset voltage limits the maximum gain to about 60 dB. For any given range, the

bandwidth is independent of the voltage-controlled gain. This system provides an underrange and overrange of 1.07 dB in all cases; for example, the overall gain is ?11.07 dB to +31.07 dB in the maximum bandwidth mode (Pin 5 and Pin 7 strapped). This X-AMP structure has many advantages over former methods of gain control based on nonlinear elements. Most importantly, the fixed-gain amplifier can use negative feedback to increase its accuracy. Because large inputs are first attenuated, the amplifier input is always small. For example, to deliver a ±1 V output in the ?1 dB/+41 dB mode (that is, using a fixed amplifier gain of 41.07 dB), its input is only 8.84 mV; therefore, the distortion can be very low. Equally important, the small-signal gain and phase response, and thus the pulse response, are essentially independent of gain.

Figure 31 is a simplified schematic. The input attenuator is a 7-section R-2R ladder network, using untrimmed resistors ofnominally R = 62.5 ?, which results in a characteristic resistance of125 ? ± 20%. A shunt resistor is included at the input and lasertrimmed to establish a more exact input resistance of 100 ? ± 3%, which ensures accurate operation (gain and HP corner frequency) when used in conjunction with external resistors or capacitors.The nominal maximum signal at input VINP is 1 V rms (±1.4 V peak) when using the recommended ±5 V supplies, although operation to ±2 V peak is permissible with some increase in HF distortion and feedthrough. Pin 4 (COMM) must be connected directly to the input ground; significant impedance in this connection reduces the gain accuracy. The signal applied at the input of the ladder network is attenuated by 6.02 dB by each section; therefore, the attenuation to each of the taps is progressively 0 dB, 6.02 dB, 12.04 dB, 18.06 dB, 24.08 dB, 30.1 dB, 36.12 dB, and 42.14 dB. A unique circuit technique is employed to interpolate between these tap points, indicated by the slider in Figure 31, thus providing continuous attenuation from 0 dB to 42.14 dB. It helps in understanding the AD603 to think in terms of a mechanical means for moving this slider from left to right; in fact, its position is controlled by the voltage between Pin 1 and Pin 2. The details of the gain control interface are in the The Gain Control Interface section.

Data Sheet

The gain is at all times very exactly determined, and a linear-in-dB relationship is automatically guaranteed by the exponential nature of the attenuation in the ladder network (the X-AMP principle). In practice, the gain deviates slightly from the ideal law, by about ±0.2 dB peak (see, for example, Figure 5).

NOISE PERFORMANCE

An important advantage of the X-AMP is its superior noise performance. The nominal resistance seen at inner tap points is 41.7 ? (one third of 125 ?), which exhibits a Johnson noise spectral density (NSD) of 0.83 nV/√Hz (that is, √4kTR) at 27°C, which is a large fraction of the total input noise. The first stage of the amplifier contributes a further 1 nV/√Hz, for a total input noise of 1.3 nV/√Hz. It is apparent that it is essential to use a low resistance in the ladder network to achieve the very low specified noise level. The source impedance of the signal forms a voltage divider with the 100 ? input resistance of the AD603. In some applications, the resulting attenuation may be unacceptable, requiring the use of an external buffer or preamplifier to match a high impedance source to the low impedance AD603.

The noise at maximum gain (that is, at the 0 dB tap) depends on whether the input is short-circuited or open-circuited. When short-circuited, the minimum NSD of slightly over 1 nV/√Hz is achieved. When open-circuited, the resistance of 100 ? looking into the first tap generates 1.29 nV/√Hz, so the noise increases to 1.63 nV/√Hz. (This last calculation would be important if the AD603 were preceded by, for example, a 900 ? resistor to allow operation from inputs up to 10 V rms.) As the selected tap moves away from the input, the dependence of the noise on source impedance quickly diminishes.

Apart from the small variations just discussed, the signal-to-noise (SNR) at the output is essentially independent of the attenuator setting. For example, on the ?11 dB/+31 dB range, the fixed gain of ×35.8 raises the output NSD to 46.5 nV/√Hz. Therefore, for the maximum undistorted output of 1 V rms and a 1 MHz bandwidth, the output SNR would be 86.6 dB, that is, 20 log(1 V/46.5 μV).

Data Sheet

VPOS8VNEG6GPOS1VGGNEG2GAIN-CONTROLINTERFACESCALINGREFERENCEPRECISIONPASSIVEINPUTATTENUATORFIXED-GAINAMPLIFIER7AD603

VOUTAD6036.44k?*5FDBK694?*0dBVINP3R–6.02dBR–12.04dB–18.06dB–24.08dBRRR–30.1dBR–36.12dB–42.14dBR20?*2R2R2R2R2R2RRCOMM4R-2R LADDER NETWORK00539-029*NOMINALVALUES.Figure 31. Simplified Block Diagram

THE GAIN CONTROL INTERFACE

The attenuation is controlled through a differential, high impedance (50 MΩ) input, with a scaling factor that is laser-trimmed to 40 dB per volt, that is, 25 mV/dB. An internal band gap reference ensures stability of the scaling with respect to supply and temperature variations.

When the differential input voltage VG = 0 V, the attenuator slider is centered, providing an attenuation of 21.07 dB. For the maximum bandwidth range, this results in an overall gain of 10 dB (= ?21.07 dB + 31.07 dB). When the control input is ?500 mV, the gain is lowered by +20 dB (= 0.500 V × 40 dB/V) to ?10 dB; when set to +500 mV, the gain is increased by +20 dB to +30 dB. When this interface is overdriven in eitherdirection, the gain approaches either ?11.07 dB (= ? 42.14 dB ++31.07 dB) or 31.07 dB (= 0 + 31.07 dB), respectively. The only constraint on the gain control voltage is that it be kept within the common-mode range (?1.2 V to +2.0 V assuming +5 V supplies) of the gain control interface.

For example, if the gain is to be controlled by a DAC providing a positive-only, ground-referenced output, the gain control low (GNEG) pin should be biased to a fixed offset of 500 mV to set the gain to ?10 dB when gain control high (GPOS) is at zero, and to 30 dB when at 1.00 V.

It is a simple matter to include a voltage divider to achieve other scaling factors. When using an 8-bit DAC having an FS output of 2.55 V (10 mV/bit), a divider ratio of 2 (generating 5 mV/bit) results in a gain-setting resolution of 0.2 dB/bit. The use of such offsets is valuable when two AD603s are cascaded, when

various options exist for optimizing the signal-to-noise profile, as is shown in the Sequential Mode (Optimal SNR) section,

PROGRAMMING THE FIXED-GAIN AMPLIFIER USING PIN STRAPPING

Access to the feedback network is provided at Pin 5 (FDBK). The user may program the gain of the output amplifier of the AD603 using this pin, as shown in Figure 32, Figure 33, and Figure 34. There are three modes: in the default mode, FDBK

The basic gain of the AD603 can therefore be calculated by is unconnected, providing the range +9 dB/+51 dB; when VOUT

and FDBK are shorted, the gain is lowered to ?11 dB/+31 dB; Gain (dB) = 40 VG +10(1)

and, when an external resistor is placed between VOUT and

where VG is in volts. When Pin 5 and Pin 7 are strapped (see the FDBK, any intermediate gain can be achieved, for example, Programming the Fixed-Gain Amplifier Using Pin Strapping ?1 dB/+41 dB. Figure 35 shows the nominal maximum gain vs. section), the gain becomes external resistor for this mode.

Gain (dB) = 40 VG + 20 for 0 to +40 dB

VC11and

Gain (dB) = 40 VG + 30 for +10 to +50 dB

The high impedance gain control input ensures minimal loading when driving many amplifiers in multiple channel or cascaded applications. The differential capability provides flexibility in choosing the appropriate signal levels and polarities for various control schemes.

(2)

VINGPOSGNEGVINPVPOS8VOUT7VNEG6VPOSVOUTVNEG00539-030AD603VC2234COMMFDBK5Figure 32. ?10 dB to +30 dB; 90 MHz Bandwidth

AD603 Data Sheet

Data Sheet

USING THE AD603 IN CASCADE

Two or more AD603s can be connected in series to achieve higher gain. Invariably, ac coupling must be used to prevent the dc offset voltage at the output of each amplifier from overloading the following amplifier at maximum gain. The required high-pass coupling network is usually just a capacitor, chosen to set the desired corner frequency in conjunction with the well-defined 100 Ω input resistance of the following amplifier. For two AD603s, the total gain control range becomes 84 dB (2 × 42.14 dB); the overall ?3 dB bandwidth of cascaded stages is somewhat reduced. Depending on the pin strapping, the gain and bandwidth for two cascaded amplifiers can range from ?22 dB to +62 dB (with a bandwidth of about 70 MHz) to +22 dB to +102 dB (with a bandwidth of about 6 MHz).There are several ways of connecting the gain control inputs in cascaded operation. The choice depends on whether it is important to achieve the highest possible instantaneous signal-to-noise ratio (ISNR), or, alternatively, to minimize the ripple in the gain error. The following examples feature the AD603 programmed for maximum bandwidth; the explanations apply to other gain/bandwidth combinations with appropriate changes to the arrangements for setting the maximum gain.

AD603

Figure 37 shows the SNR over a gain range of ?22 dB to +62 dB, assuming an output of 1 V rms and a 1 MHz bandwidth. Figure 38, Figure 39, and Figure 40 show the general connections to accomplish this. Here, both the positive gain control inputs (GPOS) are driven in parallel by a positive-only, ground-referenced source with a range of 0 V to 2 V, while the negative gain

control inputs (GNEG) are biased by stable voltages to provide the needed gain offsets. These voltages may be provided by resistive dividers operating from a common voltage reference.

90858075SNR (dB)7065605500539-035SEQUENTIAL MODE (OPTIMAL SNR)

In the sequential mode of operation, the ISNR is maintained at its highest level for as much of the gain control range as possible.

A1–40.00dB–8.93dB31.07dB50–0.20.20.61.0VC (V)1.41.82.2Figure 37. SNR vs. Control Voltage, Sequential Control (1 MHz Bandwidth)

A2–51.07dBINPUT0dB–42.14dBGPOSVG1GNEG–42.14dBGPOSVG2GNEG31.07dBVC = 0VVO1 = 0.473VVO2 = 1.526VFigure 38. AD603 Gain Control Input Calculations for Sequential Control Operation VC = 0 V

0dB31.07dBGNEGVG1VC = 1.0V31.07dB–11.07dBINPUT0dB0dBGPOS–42.14dBGPOSVG2GNEG31.07dBVO1 = 0.473VVO2 = 1.526VFigure 39. AD603 Gain Control Calculations for Sequential Control Operation VC = 1.0 V

0dB31.07dBGNEGVG1VC = 2.0V31.07dB–28.93dBINPUT0dB0dBGPOS–2.14dBGPOSVG2GNEG31.07dBVO1 = 0.473VVO2 = 1.526VFigure 40. AD603 Gain Control Input Calculations for Sequential Operation VC = 2.0 V

00539-038OUTPUT60dB00539-037OUTPUT20dB00539-036OUTPUT–20dB

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