中英文资料对照外文翻译
AT89C52 Single-chip microprocessor introduction
Selection of Single-chip microprocessor
1. Development of Single-chip microprocessor
The main component part of Single-chip microprocessor as a result of by such centralize to be living to obtain on the chip，In immediate future middle processor CPU。Storage RAM immediately﹑memoy read ROM﹑Interrupt system、Timer /'s counter along with I/O's rim electric circuit awaits the main microcomputer section，The lumping is living on the chip。Although the Single-chip microprocessor r is only a chip，Yet through makes up and the meritorous service be able to on sees，It had haveed the calculating machine system property，calling it for this reason act as Single-chip microprocessor r minisize calculating machine SCMS and abbreviate the Single-chip microprocessor。
1976Year the Inter corporation put out 8 MCS－48Set Single-chip microprocessor computer，After being living more than 20 years time in development that obtain continuously and wide-ranging application。1980Year that corporation put out high performance MCS －51Set Single-chip microprocessor。This type of Single-chip microprocessor meritorous service capacity、The addressing range wholly than early phase lift somewhat，Use also comparatively far more at the moment。1982Year that corporation put out the taller 16 Single-chip microprocessor MCS of performance once more －96Set。The Single-chip microprocessor computer development havees the
performance more and more to be improved﹑More and more distinguishings feature of strain。
2. Adopt the Single-chip microprocessor strong point Hacker use，Agileization of application。
? Have memory、Calculation and look-up meritorous service capacity。May make the apparatus bearing that the rule can not make。
? The command system is fit for the real-time control。 ? Bulk is little，Execution speed is quickly。
? Dependability is high，The antijamming capability is powerful。 ? The temperature use limit is vast。 ? Power-off protection is improved。 ? The product development cycle brief。
? Identical set is much as the necessary interface chip sort，The meritorous service be able to be completely，Be convenient for to pick up achieve the minimal system。 ? On the basis of the tall science and technology demand，Integration in common use software，Hardware （In case PL/M language，DAM's wave pattern producer，Analog switch awaits ）Application is agile。
Hence，Native is designed adoping with the Single-chip microprocessor core components designs。
3 . AT89C52 Component
AT89C52 microprocessor main function parameter：
And completely compatible with the MCS-51 product instruction and thepin The 8K byte is programmable/scratches writes Flash to dodge the fastmemory 1,000 time scratches writes the cycle Entire static operation: 0Hz - 24MHz Three levels of encryptions program memory 256×8 byte interior RAMs 32 programmable I/O lines
3 16 fixed time/counters 8 interrupt sources
Programmable serial UART channel
The low power loss is idle and falls the electricity pattern
CPU's composition
The CPU is the Single-chip microprocessor core components，It consists of that ruing the arithmetic sum controller await。 1. Arithmetic unit
The meritorous service of arithmetic unit be able to be carrying on arithmetic operation and logic operation，The half-byte may be adjust﹑The separate word length and so on the data manipulate。 2. Order counter PC
It is used for leaving second order which will the be carried out address。The address that the order points out in accordance PC brings out through the storage afterwards，The PC be able to plus 1 voluntarily，In immediate future point to the second order。 3. Order product register
Leave the instruction code in the order register。When CPU's execute instruction，Send into the order register through reading aloud the instruction code get in the order storage，Decipher queen after the decipherer，Issue the relevant control signal through fixed time against the control circuit。Complete the order meritorous service capacity.
Storage 1. Order storage
Used to leave order and form constant。As to 8751，EA＝1Hour，Slice internal procedure storage is occupied 0000H ～0When FFFH，Order storage fetch piece through the slice.
2. Data storage utensil
8751No matter the Single-chip microprocessor data storage utensil is living on the physics and the logic goes up wholly being divided into two addresss space，One act as the internal data storage，Call on the internal data storage in the way of order of MOV's，Another act as the external data storage utensil，Call on external data storage articles of daily use order of MOVX's，Addressing mode indirect addressing。
Meritorous service capacity register special.
MCS－51Latch inner place the Single-chip microprocessor、Timer、Serial port data bumpers along with different control register and the conditions register has wholly ariseed with the meritorous service capacity register special shape。TAM's address space limit included they decentralized distributions（80H～FDH）It is inside。
8751The inside particular meritorous service capacity register consists of operating the register、Register of address、The rim latch reaches to be used the interception、Count / fixed a time and the serial port administration register。
The calculation register consists of accumulator A、Register B and program mode word register PSW。
The register of address consists of indicator DPTR of warehouse indicator SP and data addresses。MCS－51The SP of Single-chip microprocessor act as 8，The place included the warehouse among the RAM is comparatively more agile。Data pointer DPTR is 16 registers，Such high position byte is expressed in the way of DPh，The position is expressed in the way of DPI，In immediate future may as 16 register DPTRs the handle，8 register DPh and DPIs who also may do worthwhile independence handle。
Port P0 ～The P3 is separately I/O port P0 ～The latch of P3。P0～P3 is as register special still usable direct addressing means participation else operating instruction operation。
Serial data bumper SBUF is used conveying either the data the receiveed
loading，In reality it is consising of two independence registers，One is transmiting the bumper，Another is receives the bumper。
AT89C52 pin explanation
The AT89C52 monolithic integrated circuit uses 40 pins the double row straightto insert the seal way.
The power source pin turns on the monolithic integrated circuit thework power source.
VCC: Meets the +5V power source. GND: Earth.
? Port 0: Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs.
Port 0 can also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode, P0 has internal pullups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes during program verification. External pullups are required during program verification.
? Port 1:Port 1 is an 8-bit bi-directional I/O port with internal pullups.The Port 1 output buffers can sink/source four TTL inputs.When 1s are written to Port 1 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups.
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.
Port 1 also receives the low-order address bytes during Flash programming and
verification.
? Port 2:Port 2 is an 8-bit bi-directional I/O port with internal pullups.The Port 2 output buffers can sink/source four TTL inputs.When 1s are written to Port 2 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups.
Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pullups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
? Port 3:Port 3 is an 8-bit bi-directional I/O port with internal pullups.The Port 3 output buffers can sink/source four TTL inputs.When 1s are written to Port 3 pins, they are pulled high by the internal pullups and can be used as inputs. As inputs,Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.
Port 3 also serves the functions of various special features of the AT89C51, as shown in the following table.
Port 3 also receives some control signals for Flash programming and verification. ? RST:Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device
? ALE/PROG:Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory.This pin is also the program pulse input (PROG) during Flash programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.
? PSEN:Program Store Enable is the read strobe to external program memory. When the AT89C52 is executing code from external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory.
? EA/VPP:External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH.Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset.
EA should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (VPP) during Flash programming when 12-volt programming is selected.
? XTAL1:Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
? XTAL2:Output from the inverting oscillator amplifier.
? Special Function Registers:A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1.
Note that not all of the addresses are occupied,and unoccupied addresses may not be implemented on the chip.Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations,since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
? Data Memory:The AT89C52 implements 256 bytes of on-chip RAM. The upper
128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.
When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space.
Timer 0 and 1:Timer 0 and Timer 1 in the AT89C52 operate the same way as Timer 0 and Timer 1 in the AT89C51.
Timer 2:Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 in the SFR T2CON (shown in Table 2).Timer 2 has three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 3.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition,the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.
AT89C52单片机介绍
1. 单片机的发展
单片机因将其主要组成部分集中在一个芯片上得名，即中央处理器CPU。存储器RAM﹑只读存储器ROM﹑中断系统﹑定时器/计数器以及I/O口电路等主要微型机部分，集中在一个芯片上。虽然单片机只是一个芯片，但从组成和功能上看，它已具有了计算机系统的属性，为此称它为单片机微型计算机SCMS简称单片机。
1976年Inter公司推出了8位的MCS－48系列单片机，在以后20多年的时间里得到了不断的发展和广泛的应用。1980年该公司推出了高性能的MCS－51系列单片机。这类单片机的功能﹑寻址范围都比早期有所提高，目前应用也比较多。1982年该公司又推出了性能更高的16位单片机MCS－96系列的。单片机发展具有性能越来越完善﹑品种越来越多的特点。
2. 采用单片机的优点
? 硬件通用化，应用灵活化。
? 具有记忆﹑计算和查表功能。可制成常规无法制成的仪器仪表。 ? 指令系统适合实时控制。 ? 体积小，执行速度快。 ? 可靠性高，抗干扰能力强。 ? 温度使用范围广。 ? 断电保护完善。 ? 产品开发周期短。
? 同一系列和配套接口芯片种类多，功能全，便于挑选来实现最小系统。 ? 根据高科技要求，集成常用软件，硬件（如PL/M,BASIC,FORTH语言，DAM波形发生器，模拟开关等）应用灵活。
因此，本设计采用以单片机位核心的部件设计。
3. AT89C52单片机的结构
AT89C52单片机主要性能参数：
? 与MCS-51产品指令和引脚完全兼容 ? 8K字节可编程/擦写Flash闪速存储器 ? 1000次擦写周期
? 全静态操作：0Hz—24MHz
三级加密程序存储器 256×8字节内部RAM 32个可编程I/O口线 3个16位定时/计数器 8个中断源
可编程串行UART通道 ? 低功耗空闲和掉电模式 3.1 CPU结构
CPU是单片机的核心部件，它由运行算术和控制器等组成。 1. 运算器
运算器的功能是进行算术运算和逻辑运算，可以对半字节﹑单字节等数据进行操作。
2. 程序计数器PC
它用来存放下一条要执行的指令的地址。当一条指令按照PC所指的地址从存储器中取出后，PC会自动加1，即指向下一条指令。
（3）指令积寄存器
指令寄存器中存放指令代码。CPU执行指令时，由程序存储器中读取的指令代码送入指令寄存器，经译码器译码后，由定时与控制电路发出相应的控制信号。完成指令功能。
3.2 存储器 1. 程序存储器
用于存放程序及表格常数。对于8751，EA＝1时，片内程序存储器占用0000H～0FFFH时，则从片外程序存储器取指令。 2. 数据存储器
8751单片机数据存储器无论在物理上和逻辑上都分为两地址空间，一个为内部数据存储器，访问内部数据存储器用MOV指令，另一个为外部数据存储器，访问外部数据存储器用MOVX指令，寻址方式间接寻址。
3.3 专用功能寄存器
MCS－51单片机内的锁存器、定时器、串行口数据缓冲器以及各种控制寄存器和状态寄存器都是以专用功能寄存器的形式出现的。它们分散的分布在内部TAM地址空间范围（80H～FDH）内。
8751内的特殊功能寄存器包括运算寄存器、地址寄存器、口锁存器及用于中断、计数/定时和串行口管理的寄存器。
运算寄存器包括累加器A﹑寄存器B及程序状态字寄存器PSW。
地址寄存器包括堆栈指示器SP和数据地址指示器DPTR。MCS－51单片机的SP为8位，堆栈在内部RAM中的位置比较灵活。数据指针DPTR是一个16位寄存器，其高位字节用DPh表示，地位用DPI表示，即可以作为一个16位寄存器DPTR来处理，也可以作为独立的8位寄存器DPh和DPI处理。
端口P0～P3分别是I/O端口P0～P3的锁存器。P0～P3作为专用寄存器还可用直接寻址方式参与其他操作指令。
? ? ? ? ? ?
串行数据缓冲器SBUF用于传送或接受的数据的存放，它实际上是由两个独立的寄存器组成，一个是发送缓冲器，另一个是接收缓冲器。
3.4 AT89C52引脚说明
AT89C52单片机采用40 引脚的双列直插封装方式。 电源引脚接入单片机的工作电源。 VCC：接+5V电源。 GND：接地。
? P0口：P0口是一组8位漏极开路型双向I/O口，也即地址/数据总线复用口。作为输出口用时，每位能吸收电流的方式驱动8个TTL逻辑门电路，对端口P0写“1”时，可作为高阻抗输入端用。
在访问外部数据存储器或程序存储器时，这组口线分时转换地址（低8位）和数据总线复用，在访问期间激活内部上拉电阻。
在Flash编程时，P0口接受指令字节，而在程序校验时，输出指令字节，校验时，要求外接上拉电阻。
? P1口：P1是一个带内部上拉电阻的8位双向I/O口，P1的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流。
与AT89C51不同之处是，P1.0和P1.1还可分别作为定时/计数器2的外部计数输入（P1.0/T2）和输出（P1.1/T2EX），
Flash编程和程序校验期间，P1接收低8位地址。
? P2口：P2是一个带有内部上拉电阻的8位双向I/O口，P2的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对P2端口写“1”，通过内部的上拉电阻把端口拉到高电平，此时可作输入口。作输入口使用时，因为内部存在上拉电阻，某个引脚被外部信号拉低时会输出一个电流。
在访问外部程序存储器或16位地址的 外部数据存储器时，P2口送出高8位地址数据。在访问8位地址的外部数据存储器时，P2口输出P2锁存器的内容。 Flash编程或校验时，P2亦接收高位地址和一些控制信号。
? P3口：P3是一个带有内部上拉电阻的8位双向I/O口，P3的输出缓冲级可驱动（吸收或输出电流）4个TTL逻辑门电路。对P3端口写“1”，它们被内部上拉电阻拉高并可作为输入端口。此时，被外部拉低的P3口将用上拉电阻输出电流。 P3口除了作为一般的I/O口线外，更重要的用途是它的第二功能.
此外，P3口还接收一些Flash闪速存储器编程和程序校验的控制信号。
? RST：复位输入。当振荡器工作时，RST引脚出现两个周期以上高电平将使单片机复位。
? ALE/PROG：当访问外部程序存储器或数据存储时，ALE地址锁存允许输出脉冲用于锁存地址的低8位字节。一般情况下，ALE仍以时钟振荡频率的1/6输出固定的脉冲信号，因此它可对外输出时钟或用于定时目的。要注意的是：每当访问外部数据存储器时将跳过一个ALE脉冲。
对Flash存储器编程期间，该引脚还用于输入编程脉冲PROG。
如有必要，可通过对特殊功能寄存器SFR区中的8EH单元的D0位置位，可禁止ALE操作。该位置位后，只有一条MOVX和MOVC指令才能将ALE激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置禁止位ALE无效。
? PSEN：程序储存允许PSEN输出是外部程序存储器的读选通信号，当AT89C52由外部程序存储器取指令或数据时，每个机器周期两次PSEN有效，即输出两个脉冲。在此期间，当访问外部数据存储器，将跳过两次PSEN信号。
? EA/VPP：外部访问允许。欲使CPU仅访问外部程序存储器地址为0000H—FFFFH，EA端必须保持低电平接地。需注意的是：如果加密位LB1被编程，复位时内部会锁存EA端状态。
如EA端为高电平接Vcc端，CPU则执行内部程序存储器中的指令。
Flash存储器编程时，该引脚加上+12V的编程允许电压Vpp，当然这必须是该器件是使用12V编程电压Vpp。
? XTAL1：振荡器反相放大器及内部时钟发生器的输入端。 ? XTAL2：振荡器反相放大器的输出端。
? 特殊功能寄存器：在AT89C52片内存储器中，80H-FFH共128个单元为特殊功能寄存器SFR。
并非所有的地址都被定义，从80H-FFH共128个字节只有一部分被定义，还有相当一部分没有定义。对没有定义的单元读写是无效的，读出的数值将不确定，而写入的数据也将丢失。
不应将数据“1”写入未定义的单元，由于这些单元在将来的产品中可能赋予新的功能，在这种情况下，复位后这些单元数值总是“0”。
? 数据存储器：AT89C52有256个字节的内部RAM，80H-FFH高128个字节与特殊寄存器SFR地址是重叠的，也就是高128字节的RAM和特殊功能寄存器的地址是相同的，但物理上它们是分开的。
当一条指令访问7FH以上的内部地址单元时，指令中的寻址方式是不同的，也即寻址方式决定是访问高128字节RAM还是访问特殊功能寄存器。如果指令是直接寻址方式则为访问特殊功能寄存器。
? 定时器0和定时器1：AT89C52的定时器0和定时器1的工作方式与AT89C51相同。
? 定时器2：定时器2是一个16位定时/计数器。它既可当定时器使用，也可作为外部事件计数器使用，其工作方式由特殊功能寄存器T2CON的C/T2位选择。定时器2有但种工作方式，捕获方式，自动重装载向上或向下计数方式和波特率发生器方式，工作方式由T2CON的控制位来选择。
定时器2由两个8位寄存器TH2和TL2组成，在定时器工作方式中，每个机器周期TL2寄存器的值加1，由于一个机器周期由12个振荡时钟构成，因此，计数速率为振荡频率的1/12。
在计数工作方式时，当T2引脚上外部输入信号产生由1到0的下降沿时，寄存器的值加1，在这种工作方式下，每个机器周期的5SP2期间，对外部输入进行采样。若在第一个周期中采到的值为1，而在下一个周期中的采到的值为0，则在紧跟着的下一个周期的S3P1期间寄存器加1，由于识别1到0的跳变需要2个机器周期24个振荡周期，因此，最高计数速率为振荡周期的1/24，为确保采样的正确性，要求输入的电平在变化前至少保持一个完整周期的时间，以保证输入信号至少被采样一次。
致 谢
本次设计是在余副教授的亲切关怀和悉心指导下完成的。他严肃的科学态度，严谨的治学精神，精益求精的工作作风，深深地感染和激励着我。从课题的选择到设计的最终完成，余老师都始终给予我细心的指导和不懈的支持。两年多来，余老师不仅在学业上给我们以精心指导，同时还在思想、生活上给我们以无微不至的关怀，在此谨向余老师致以诚挚的谢意和崇高的敬意。
在此，我还要感谢在一起愉快度过大学生活的各位同学，正是由于你们的帮助和支持，我才能克服一个一个的困难和疑惑，直至本设计的顺利完成。特别感谢我的同宿舍同学，他们对本设计做了不少工作，给予我不少的帮助。
在设计即将完成之际，我的心情无法平静，从开始进入课题到设计的顺利完成，有很多的老师、同学、朋友给了我无言的帮助，在这里请接受我诚挚的谢意!最后我还要感谢培养我长大含辛茹苦的父母，谢谢你们!
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