VerilogHDL汽车尾灯控制器的设计

熊雄 汽车尾灯控制器的设计 第15页 共16页 END ART;

3右边灯控制模块 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY RC IS

PORT(CLK,RP,LR,BRAKE,NIGHT:IN STD_LOGIC; LEDR,LEDB,LEDN: OUT STD_LOGIC); END;

ARCHITECTURE ART OF RC IS BEGIN

LEDB<=BRAKE; LEDN<=NIGHT;

PROCESS(CLK,RP,LR) BEGIN

IF CLK'EVENT AND CLK = '1' THEN IF(LR = '0')THEN IF(RP = '0')THEN LEDR <='0'; ELSE

LEDR <= '1'; END IF; ELSE

LEDR <='0'; END IF; END IF; END PROCESS; END ART;

4左边灯控制模块 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY LC IS

PORT(CLK,LP,LR,BRAKE,NIGHT:IN STD_LOGIC; LEDL,LEDB,LEDN: OUT STD_LOGIC); END;

ARCHITECTURE ART OF LC IS BEGIN

LEDB<=BRAKE; LEDN<=NIGHT; PROCESS(CLK,LP,LR) BEGIN

IF CLK'EVENT AND CLK = '1' THEN IF(LR ='0')THEN IF(LP = '0')THEN LEDL<='0'; ELSE

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熊雄 汽车尾灯控制器的设计 第16页 共16页 16

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LEDL<='1'; END IF; ELSE

LEDL <='0'; END IF; END IF; END PROCESS; END ART;