SPI Interfaces
Table 43:SPI Master Mode Interface Switching Characteristics(1)
SymbolTDCMSPICLKTMSPIDCKTMSPICKDTMSPICKOTMSPISSCLKTMSPICLKSSFMSPICLKFSPI_REF_CLKNotes:
1.
Test conditions: LVCMOS33, slow slew rate, 8mA drive strength, 15pF loads.
Description
SPI master mode clock duty cycleInput setup time for SPI{0,1}_MISOInput hold time for SPI{0,1}_MISO
Output delay for SPI{0,1}_MOSI and SPI{0,1}_SSSlave select asserted to first active clock edgeLast active clock edge to slave select deassertedSPI master mode device clock frequencySPI reference clock frequency
Min–2.008.20–3.1010.5––
Typ50–––––––
Max–––3.90––50.00200.00
Units%nsnsns
FSPI_REF_CLK cyclesFSPI_REF_CLK cycles
MHzMHz
X-Ref Target - Figure 12SPI{0,1}_SSTMSPISSCLKSPI{0,1}_CLK (CPOL=0)TMSPICLKSSSPI{0,1}_CLK (CPOL=1)TMSPICKOSPI{0,1}_MOSIDnDn–1TMSPICKDDn–2Dn–3D0TMSPIDCKSPI{0,1}_MISODnDn–1Dn–2DS191_10_022013Figure 12:SPI Master (CPHA=0) Interface Timing Diagram
X-Ref Target - Figure 13SPI{0,1}_SSSPI{0,1}_CLK (CPOL=0)TMSPISSCLKTMSPICLKSSSPI{0,1}_CLK (CPOL=1)TMSPICKOSPI{0,1}_MOSIDnDn–1TMSPICKDDn–2Dn–3D0TMSPIDCKSPI{0,1}_MISODnDn–1Dn–2Dn–3D0DS191_11_022013Figure 13:SPI Master (CPHA=1) Interface Timing Diagram
DS191 (v1.18.1) July 2, 2018Product Specification
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
DS191 (v1.18.1) July 2, 2018Product Specification
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
PL Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in the PL. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject to the same guidelines as the AC Switching Characteristics, page15. In each table, the I/O bank type is either High Performance (HP) or High Range (HR).
Table 52:PL Networking Applications Interface Performances
Description
SDR LVDS transmitter (using OSERDES; DATA_WIDTH=4 to 8)DDR LVDS transmitter (using OSERDES; DATA_WIDTH=4 to 14)SDR LVDS receiver (SFI-4.1)(1)DDR LVDS receiver (SPI-4.2)(1)
I/O Bank TypeHRHPHRHPHRHPHRHP
Speed Grade
-3E7107101250160071071012501600
-2E/-2I/-2LI
7107101250140071071012501400
-1C/-1I62562595012506256259501250
-1Q/-1LQ62562595012506256259501250
UnitsMb/sMb/sMb/sMb/sMb/sMb/sMb/sMb/s
Notes:
1.
LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominatedeterministic performance.
Table53 provides the maximum data rates for applicable memory standards using the Zynq-7000SoC memory PHY. The final performance of the memory interface is determined through a complete design implemented in the Vivado or ISE Design Suite, following guidelines in the Zynq-7000 SoC and 7Series Devices Memory Interface Solutions User Guide (UG586).
DS191 (v1.18.1) July 2, 2018Product Specification
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
DS191 (v1.18.1) July 2, 2018Product Specification
Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics
Table 25:PS Reset/Power Supply Timing Requirements
SymbolTSLW(1)
Description
128KB CRC eFUSE disabled and PLL enabled.Default configuration
PS_CLK Frequency
(MHz)
3033.33603033.3360
Min121213–32–27–9–19–16–3–830–746–408
Max39404013132591225–788–705–374
Unitsmsmsmsmsmsmsmsmsmsmsmsms
128KB CRC eFUSE disabled and PLL in bypass.
128KB CRC eFUSE enabled and PLL enabled.(2)
3033.3360
128KB CRC eFUSE enabled and PLL in bypass.(2)
3033.3360
Notes:
1.2.
Valid for power supply ramp times of less than 6ms. For ramp times longer than 6ms, see the BootROM Performance section of theZynq-7000SoC Technical Reference Manual (UG585).
If any PS and PL power supplies are tied together, observe the PS_POR_B assertion time requirement (TPSPOR) in Table24 and itsaccompanying note.
PS Configuration
Table 26:Processor Configuration Access Port Switching Characteristics
SymbolFPCAPCK
Description
Maximum processor configuration access port (PCAP) frequency
Min–
Typ–
Max100
UnitsMHz
DDR Memory Interfaces
Table 27:DDR3 Interface Switching Characteristics (1333Mb/s)(1)
SymbolTDQVALID(2)TDQDS(3)TDQDH(4)TDQSSTCACK(5)TCKCA(6)
Input data valid windowOutput DQ to DQS skewOutput DQS to DQ skewOutput clock to DQS skew
Command/address output setup time with respect to CLKCommand/address output hold time with respect to CLK
DescriptionMin45095222–0.11465528
Max–––0.08––
UnitspspspsTCKpsps
DS191 (v1.18.1) July 2, 2018Product Specification
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