电子元器件芯片AD8529AR中文规格书

Data Sheet TEST CIRCUITS

ENVCCA0.1μFADG3304

ADG3304VCCY0.1μFENAYK2VCCA0.1μFADG3304VCCY0.1μFK1GNDAYAKIOHIOL04860-04604860-043GNDFigure 29. VOH/VOL Voltages at Pin A Figure 32. Three-State Leakage Current at Pin Y

ENVCCA0.1μFADG3304VCCY0.1μFVCCAK2AYADG3304VCCY0.1μF0.1μFK1GNDAYIOHIOL04860-044AKENGND04860-047Figure 30. VOH/VOL Voltages at Pin Y Figure 33. EN Pin Leakage Current

ENVCCA0.1μFADG3304VCCY0.1μFENVCCAADG3304VCCYAKAYACAPACITANCEMETERYGND04860-045GND04860-048Figure 31. Three-State Leakage Current at Pin A Figure 34. Capacitance at Pin A

Rev. E | Page 13 of 21

ADG3304 TERMINOLOGY

VIHA

Logic input high voltage at Pin A1 to Pin A4. VILA

Logic input low voltage at Pin A1 to Pin A4. VOHA

Logic output high voltage at Pin A1 to Pin A4. VOLA

Logic output low voltage at Pin A1 to Pin A4. CA

Capacitance measured at Pin A1 to Pin A4 (EN = 0). ILA, Hi-Z

Leakage current at Pin A1 to Pin A4 when EN = 0 (high impedance state at Pin A1 to Pin A4). VIHY

Logic input high voltage at Pin Y1 to Pin Y4. VILY

Logic input low voltage at Pin Y1 to Pin Y4. VOHY

Logic output high voltage at Pin Y1 to Pin Y4. VOLY

Logic output low voltage at Pin Y1 to Pin Y4. CY

Capacitance measured at Pin Y1 to Pin Y4 (EN = 0). ILY, Hi-Z

Leakage current at Pin Y1 to Pin Y4 when EN = 0 (high impedance state at Pin Y1 to Pin Y4). VIHEN

Logic input high voltage at the EN pin. VILEN

Logic input low voltage at the EN pin. CEN

Capacitance measured at EN pin. ILEN

Enable (EN) pin leakage current.

tEN

Three-state enable time for Pin A1 to Pin A4 and Pin Y1 to Pin Y4.

tP, A→Y

Propagation delay when translating logic levels in the A→Y direction.

tR, A→Y

Rise time when translating logic levels in the A→Y direction.

Data Sheet

TF, A→Y

Fall time when translating logic levels in the A→Y direction. DMAX, A→Y

Guaranteed data rate when translating logic levels in the A→Y direction under the driving and loading conditions specified in Table 1.

TSKEW, A→Y

Difference between propagation delays on any two channels when translating logic levels in the A→Y direction.

tPPSKEW, A→Y

Difference in propagation delay between any one channel and the same channel on a different part (under same driving/ loading conditions) when translating in the A→Y direction. tP, Y→A

Propagation delay when translating logic levels in the Y→A direction.

tR, Y→A

Rise time when translating logic levels in the Y→A direction. tF, Y→A

Fall time when translating logic levels in the Y→A direction. DMAX, Y→A

Guaranteed data rate when translating logic levels in the Y→A direction under the driving and loading conditions specified in Table 1.

tSKEW, Y→A

Difference between propagation delays on any two channels when translating logic levels in the Y→A direction.

tPPSKEW, Y→A

Difference in propagation delay between any one channel and the same channel on a different part (under the same driving/ loading conditions) when translating in the Y→A direction. VCCA

VCCA supply voltage. VCCY

VCCY supply voltage. ICCA

VCCA supply current. ICCY

VCCY supply current.

IHi-Z, A

VCCA supply current during three-state mode (EN = 0). IHi-Z, Y

VCCY supply current during three-state mode (EN = 0).

Rev. E | Page 16 of 21