SIII51001-1.8
The Stratix?III family provides one of the most architecturally advanced, high-performance, low-power FPGAs in the marketplace.
StratixIII FPGAs lower power consumption through Altera’s innovative Programmable Power Technology, which provides the ability to turn on the
performance where needed and turn down the power consumption for blocks not in use. Selectable Core Voltage and the latest in silicon process optimizations are also employed to deliver the industry’s lowest power, high-performance FPGAs. Specifically designed for ease of use and rapid system integration, the StratixIII FPGA family offers two variants optimized to meet different application needs:
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The StratixIII L family provides balanced logic, memory, and multiplier ratios formainstream applications.
The StratixIII E family is memory- and multiplier-rich for data-centricapplications.
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Modular I/O banks with a common bank structure for vertical migration lend
efficiency and flexibility to the high-speed I/O. Package and die enhancements with dynamic on-chip termination, output delay, and current strength control provide best-in-class signal integrity.
Based on a 1.1-V, 65-nm all-layer copper SRAM process, the StratixIII family is a programmable alternative to custom ASICs and programmable processors for high-performance logic, digital signal processing (DSP), and embedded designs.StratixIII devices include optional configuration bit stream security through volatile or non-volatile 256-bit Advanced Encryption Standard (AES) encryption. Where ultra-high reliability is required, StratixIII devices include automatic error detection circuitry to detect data corruption by soft errors in the configuration random-access memory (CRAM) and user memory cells.
Features Summary
StratixIII devices offer the following features:
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48,000 to 338,000 equivalent logic elements (LEs) ( refer to Table1–1)2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAMblock sizes to implement true dual-port memory and FIFO buffers
High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18,and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, andfinite impulse response (FIR) filters
I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling forrobust signal integrity
Programmable Power Technology, which minimizes power while maximizingdevice performance
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Chapter 1:StratixIII Device Family OverviewFeatures Summary
Table1–1 lists the StratixIII FPGA family features.
Table1–1.FPGA Family Features for StratixIII Devices
Device/ FeatureEP3SL50EP3SL70
StratixIII Logic Family
EP3SL110EP3SL150EP3SL200EP3SL340EP3SE50
StratixIII Enhanced Family
EP3SE80EP3SE110EP3SE260
Notes to Table1–1:
ALMs19K27K43K57K80K135K19K32K43K102K
LEs47.5K67.5K107.5K142.5K200K337.5K47.5K80K107.5K255K
M9K Blocks1081502753554681,040400495639864
Total
M144K MLAB
Embedded
BlocksBlocks
RAM Kbits661216364812121648
9501,3502,1502,8504,0006,7509501,6002,1505,100
1,8362,2144,2035,4999,39616,2725,3286,1838,05514,688
MLAB RAM Kbits (1)2974226728911,2502,1092975006721,594
Total RAM Kbits(2)2,1332,6364,8756,39010,64618,3815,6256,6838,72716,282
18×18-bit Multipliers(FIR Mode)
216288288384576576384672896768
PLLs (3)4488121248812
Stratix III Device Handbook, Volume 1
Chapter 1:StratixIII Device Family Overview
Features Summary
Stratix III Device Handbook, Volume 1
Chapter 1:StratixIII Device Family OverviewFeatures Summary
Table1–4 lists the StratixIII Hybrid FineLine BGA (HBGA) package sizes.Table1–4.Hybrid FineLine BGA Package Sizes
Dimension
Pitch (mm)Area (mm2)
Length/Width (mm?mm)
780 Pin1.001,08933/33
1152 Pin1.001,60040/40
StratixIII devices are available in up to three speed grades: –2, –3, and –4, with –2 being the fastest. StratixIII devices are offered in both commercial and industrial temperature range ratings with leaded and lead-free packages. Selectable Core
Voltage is available in specially marked low-voltage devices (L ordering code suffix).Table1–5 lists the StratixIII device speed grades.
Table1–5.Speed Grades for StratixIII Devices(Part 1 of 2)
TemperatureGrade
CommercialIndustrial
EP3SL70
CommercialIndustrial
EP3SL110
CommercialIndustrial
EP3SL150
CommercialIndustrial
EP3SL200
CommercialIndustrial (1)
EP3SL340
CommercialIndustrial (1)CommercialIndustrial
EP3SE80
CommercialIndustrial
EP3SE110
CommercialIndustrial
Device
484 -PinFineLineBGA
–2, –3, –4,–4L–3, –4, –4L–2, –3, –4,–4L–3, –4, –4L
————————–2, –3, –4,–4L–3, –4, –4L
————
780-PinFineLineBGA
–2, –3,–4,–4L–3, –4, –4L–2, –3, –4, –4L–3, –4, –4L–2, –3, –4, –4L–3, –4, –4L–2,–3, –4,–4L–3, –4, –4L
————–2, –3, –4, –4L–3, –4, –4L–2, –3, –4, –4L–3, –4, –4L–2,–3, –4,–4L–3, –4, –4L
780-PinHybridFineLineBGA
————————–2,–3, –4, –4L–3, –4, –4L
————————
1152-Pin FineLineBGA
————–2, –3, –4,–4L–3, –4, –4L–2, –3, –4,–4L–3, –4, –4L–2,–3, –4,–4L–3, –4, –4L
————–2, –3, –4,–4L–3, –4, –4L–2, –3, –4,–4L–3, –4, –4L
1152-PinHybridFineLineBGA
——————————–2, –3, –4–3, –4, –4L
——————
1517-PinFineLineBGA
————————–2,–3, –4,–4L–3, –4, –4L–2, –3, –4–3, –4, –4L
——————
1760-PinFineLineBGA
——————————–2, –3, –4–3, –4, –4L
——————
EP3SL50
EP3SE50
Stratix III Device Handbook, Volume 1
Chapter 1:StratixIII Device Family Overview
Architecture Features
Table1–5.Speed Grades for StratixIII Devices(Part 2 of 2)
TemperatureGrade
CommercialIndustrial (1)
Device
484 -PinFineLineBGA
——
780-PinFineLineBGA
——
780-PinHybridFineLineBGA
–2, –3, –4,–4L–3, –4, –4L
1152-Pin FineLineBGA
–2,– 3, –4,–4L–3, –4, –4L
1152-PinHybridFineLineBGA
——
1517-PinFineLineBGA
–2, –3, –4,–4L–3, –4,–4L
1760-PinFineLineBGA
——
EP3SE260
Stratix III Device Handbook, Volume 1
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