EDA技术实验报告

5、通过QuartusII集成环境，将设计下载到实验电路上进行硬件测试。 管脚锁定：

Clk clk1 43

fx

(频率任选)

A(7): 81 SEG dp A(6): PIO6 11 SEG g A(5): PIO5 10 SEG f A(4): PIO4 9 SEG e A(3): PIO3 8 SEG d A(2): PIO2 7 SEG c A(1): PIO1 6 SEG b A(0): PIO0 5 SEG a S(1): 79 S(0): 78

四、思考题：

本实验中的控制器部分可以用以前实验中的哪个电路来实现，其输出的rst和ena信号是否可以合

并为一个信号？

实验结果：

各模块电路的VHDL描述：

测试控制电路: LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.all; USE IEEE.STD_LOGIC_UNSIGNED.all; ENTITY CNT10 IS

PORT (en,clk,rst:IN STD_LOGIC;

cq:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); cout:OUT STD_LOGIC); END CNT10;

ARCHITECTURE behav OF CNT10 IS BEGIN

process(clk,en)

variable cqi :STD_LOGIC_VECTOR(3 downto 0):=\

29 begin

if (rst = '1') then CQI:=(others =>'0'); elsif(clk'event and clk = '1') then if en='1' then

if cqi<9 then cqi:= cqi+1; else cqi:=(others=>'0'); end if; end if; end if;

if cqi=9 then cout<='1'; else cout <='0'; end if; cq <= cqi; end process; END behav; 16位锁存器: LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.all; ENTITY REG16D IS PORT (lk:IN STD_LOGIC;

din:in STD_LOGIC_VECTOR(15 downto 0); dout:OUT STD_LOGIC_VECTOR(15 downto 0)); END ENTITY REG16D;

ARCHITECTURE fd1 OF REG16D IS BEGIN

process(lk,din) begin

if (lk'event and lk = '1' ) then dout<=din; end if;

30 end process;

END ARCHITECTURE fd1; 16位计数器: LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.all; ENTITY couter16D IS

PORT (fin,enabl,clr:IN STD_LOGIC;

dout:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END entity couter16D;

ARCHITECTURE fd1 OF couter16D IS COMPONENT CNT10

PORT (en,clk,rst:IN STD_LOGIC;

cq:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); cout:OUT STD_LOGIC); END COMPONENT;

SIGNAL x,y,z:STD_LOGIC; BEGIN

u1:CNT10 PORT MAP(clk=>fin,en=>enabl,rst=>clr,cq=>dout(3 downto 0),cout=>x); u2:CNT10 PORT MAP(clk=>x,en=>enabl,rst=>clr,cq=>dout(7 downto 4),cout=>y); u3:CNT10 PORT MAP(clk=>y,en=>enabl,rst=>clr,cq=>dout(11 downto 8),cout=>z); u4:CNT10 PORT MAP(clk=>z,en=>enabl,rst=>clr,cq=>dout(15 downto 12)); END ARCHITECTURE fd1;

顶层电路的VHDL描述：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.all; ENTITY freqtest IS

PORT (clk1hz,fsin:IN STD_LOGIC;

d:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END entity freqtest;

31 ARCHITECTURE fd1 OF freqtest IS COMPONENT couter16D IS

PORT (fin,enabl,clr:IN STD_LOGIC;

dout:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)); END COMPONENT; COMPONENT FTCTRL IS PORT (clkk:IN STD_LOGIC; cnt_en:out STD_LOGIC; rst_cnt:OUT STD_LOGIC; load:out std_logic); END COMPONENT; COMPONENT REG16D IS PORT (lk:IN STD_LOGIC;

din:in STD_LOGIC_VECTOR(15 downto 0); dout:OUT STD_LOGIC_VECTOR(15 downto 0)); END COMPONENT;

SIGNAL x,y,z:STD_LOGIC;

SIGNAL e:STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN

u1:couter16D PORT MAP(fin=>fsin,enabl=>x,clr=>y,dout=>e); u2:FTCTRL PORT MAP(clkk=>clk1hz,cnt_en=>x,rst_cnt=>y,load=>z); u3:REG16D PORT MAP(din=>e,lk=>z,dout=>d); --u4:DECL7S PORT MAP(A=>o0,LED7S=>do0); --u5:DECL7S PORT MAP(A=>o1,LED7S=>do1); --u6:DECL7S PORT MAP(A=>o2,LED7S=>do2); --u7:DECL7S PORT MAP(A=>o3,LED7S=>do3); END ARCHITECTURE fd1; 仿真波形：

32