EDA设计基础实验课程论文
题 目学 院专业班级学生姓名指导教师
基于verilog HDL 的数字计时器的设计
通信与电子工程学院
电子081班
大彬哥
大力会
2013 年 6月 12 日
EDA设计基础实验课程论文
摘 要
当前电子系统的设计正朝着速度快，容量大，体积小，质量轻，用电省的方向发展。推动该潮流迅速发展的决定性因素就是使用了现代化的 EDA 设计工具。本论文先确定了系统的逻辑功能，建立算法流程，选择电路结构，然后确定并设计电路所需的数据处理以及控制模块，在 Quartus II 上以verilog HDL为系统逻辑描述方法完成了数字计时器所需的按键输入消抖模块，控制模块，分频模块，计数模块，存储器模块，显示译码模块的设计与顶层设计和引脚分配，并讨论了 FPGA 设计中的常见的毛刺及其消除方法以及系统资源优化，利用计算机的强大运算能力在 Quartus II 上对用 VHDL 建模的复杂数字逻辑进行编译，自动综合地完成逻辑编译、逻辑化简、逻辑分割、逻辑综合及优化、逻辑行局布线、逻辑仿真，生成符合要求且在电路结构上可以实现的数字逻辑网表（Netlist），根据网表和某种工艺的器件自动生成具体电路，然后生成该工艺条件下这种具体电路的延时模型，并下载到 FPGA板上实际验证，通过本设计对数字系统自动化的基本概念、基本原理、特性及实现方法都有了较好的了解和理解，同时锻炼了计算机应用能力和 verilog HDL 语言的编程能力和 Quartus II 以及 MaxplusII 的使用能力，本设计圆满完成了用 verilog HDL 语言设计 1/10秒数字计时器并仿真和实际下载到 ALTERA 公司的 Cyclone II 系列的 EP2C8Q208C 中实现。
关键词：电子设计自动化，现场可编程门阵列/复杂可编程逻辑器件，硬件描述语言，数字系统设计。
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EDA设计基础实验课程论文
Abstract
The current design of electronic systems is developing to fast speed, large capacity, small size, light weight, Low power consumption. What decisively promote the rapid development of this trend is the use of modern EDA design tools. In this thesis, we firstly determine the system's logic functions, build the algorithm of system, and select the circuit, then Identify and design the data processing and control module circuit requires. Complete the key input debounce module, control
module, frequency modules, counter modules, memory modules, display decoding module digital timer requires with verilog HDL in Quartus II, and finish the design of top-level entity and Pin assignment. Discuss the reason of glitch and the elimination of glitch in FPGA.Automatically complete compile logic, logic simplification, logic partitioning, logic synthesis and logic optimization, logic board wiring, logic simulation, generate the digital logic netlist which meets the requirements and can be implemented on the circuit, automatically generate a specific circuit according to the netlist and the device. and then build this specific delay model circuit under these conditions,then download to the FPGA board and actually verify the design. Through this design, we have better knowledge and understanding for EDA's basic concepts, basic principles, characteristics and methods, also improve the ability of using computer and Quartus II and Maxplus II and Verilog HDL programming ability. The design of digital timer based on Verilog HDL is completed successfully and has been simulated and downloaded to ALTERA's EP2C8Q208C and works Successfully.
Key Words：EDA, FPGA/CPLD, verilog HDL, Digital System Design.
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EDA设计基础实验课程论文
目录
摘 要..................................................................... I 第一章 引 言 ............................................................................................................................................. 1 1.1 EDA 现状 ....................................................................................................................................... 1
1.2 硬件描述语言....................................................... 2 1.3 设计指标........................................................... 4 第 2 章 EDA设计方法及其应用 .......................................................................................................... 5
2.1 分析方法........................................................... 5 2.2 描述方法........................................................... 6 2.3 实现方法........................................................... 7 第 3 章 设计思想与方案论证 ............................................................................................................. 8
3.1 设计思想........................................................... 8 3.2 论证分析........................................................... 8 第 4 章 系统设计 .................................................................................................................................. 10
4.1 顶层电路设计...................................................... 10 4.2 数字秒表的设计原理................................................ 10 4.3 键输入消抖模块.................................................... 11 4.4 时钟分频电路模块.................................................. 12 4.5 控制电路模块...................................................... 12 4.6 计时电路模块...................................................... 13 4.7 模式选择模块...................................................... 15 4.8 存储器模块........................................................ 15 4.9 动态扫描译码显示模块.............................................. 15 第5章 程序设计.......................................................... 17 第 6 章 仿真下载实现..................................................... 20 参考文献 .................................................................................................................................................... 23
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