基于FPGA和STM32的数据采集系统设计 - 图文

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TxD <= TxD_dataReg[6]; end

4'b1111: if(BaudTick) begin

state <= 4'b0010; // bit 7 TxD <= TxD_dataReg[7]; end

4'b0010: if(BaudTick) begin

state <= 4'b0011; // stop1 TxD <= 1'b1; end

4'b0011: if(BaudTick) begin

state <= 4'b0000; // stop2 TxD <= 1'b1; end

default: if(BaudTick) begin state <= 4'b0000; TxD <= 1'b1; end endcase endmodule

2 串口接收和控制程序

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module uart_232_rx(sys_clk,sys_rst_n,uart_rxd,LED, pwm1,pwm2,A1,B1,sel ); input sys_clk ; //system clock;

input sys_rst_n ; //system reset, low is active; input uart_rxd ; //uart rxd input ; //output ports

output reg [7:0] LED ; output[4:0] pwm1,pwm2; output A1,B1;

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output[2:0] sel; //频率选择 reg [7:0] buff ; reg [7-1:0] data_out ; reg

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uart_rxd_dly1,uart_rxd_dly4,uart_rxd_dly2,uart_rxd_dly3;//uart rxd input ; reg rxd_negdge_sig_dly1 ; reg [15:0] counter ; wire rxd_negdge_sig ;

always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) begin uart_rxd_dly1 <= 1'b0; uart_rxd_dly2 <= 1'b0;

uart_rxd_dly3 <= 1'b0; uart_rxd_dly4 <= 1'b0; end else begin

uart_rxd_dly1 <= uart_rxd ; uart_rxd_dly2 <= uart_rxd_dly1;

uart_rxd_dly3 <= uart_rxd_dly2; uart_rxd_dly4 <= uart_rxd_dly3; end end

assign rxd_negdge_sig = (~uart_rxd_dly3) & uart_rxd_dly4;

always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0)

rxd_negdge_sig_dly1 <= 1'b0; else

rxd_negdge_sig_dly1 <= rxd_negdge_sig;

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end

always @(posedge sys_clk or negedge sys_rst_n) begin if ( sys_rst_n == 1'b0 ) counter <= 16'b0;

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else if ( rxd_negdge_sig_dly1 == 1'b1 && counter > 57200 ) counter <= 16'b0;

else if ( counter <= 57200 ) counter <= counter + 16'b1; else ; end

reg[4:0] pwm1,pwm2; reg[2:0] sel;

reg A1,B1,rd_instru_en;

always @(posedge sys_clk or negedge sys_rst_n) begin if ( sys_rst_n == 1'b0 ) begin buff <= 8'b0;

LED <= 8'b0;

end

else begin

rd_instru_en<=0;

case ( counter )

7800 : buff[0] <= uart_rxd_dly4 ; 13000 : buff[1] <= uart_rxd_dly4 ; 18200 : buff[2] <= uart_rxd_dly4 ; 23400 : buff[3] <= uart_rxd_dly4 ; 28600 : buff[4] <= uart_rxd_dly4 ; 33800 : buff[5] <= uart_rxd_dly4 ; 39000 : buff[6] <= uart_rxd_dly4 ; 44200 : buff[7] <= uart_rxd_dly4 ;

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endcase

if(counter>57200) begin

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default : buff <= buff ;

LED <= buff;

rd_instru_en<=1;

end

end end

always @(posedge rd_instru_en) if (sys_rst_n ==1'b0) begin pwm1<=5'b00000; pwm2<=5'b00000; // LED1<=8'b00000000; end

else begin

if (LED==8'b01000000 ) pwm1<=pwm1+5'b00001; else if ( LED==8'b00000001) pwm2<=pwm2+5'b00001;

else if ( LED==8'b00000010) A1<=0; else if ( LED==8'b00000100) A1<=1; else if ( LED==8'b00001000)B1<=0; else if ( LED==8'b00010000)B1<=1; else if ( LED==8'b00100000) sel<=sel+1; end

Endmodule 2 PWM输出程序

module PWM1 ( clk,rst_n,duty_cycle1,duty_cycle2, pwm1,pwm2); input clk; //system clock;

input rst_n; //system reset, low is active; input[4:0] duty_cycle1,duty_cycle2;