基于FPGA和STM32的数据采集系统设计 - 图文

本科毕业设计

output pwm1,pwm2; //reg define

reg pwm_out1,pwm_out2; reg [15:0] counter1,counter2; //wire define wire pwm1,pwm2;

always @(posedge clk or negedge rst_n) if (rst_n ==1'b0) begin counter1 <= 16'b0;

counter2 <= 16'b0; end

第 41 页 共 42 页

else

begin

counter1 <= counter1 + 16'b11000;

counter2 <= counter2 + 16'b11000;

end

always @(posedge clk or negedge rst_n) begin if (rst_n ==1'b0) pwm_out1 <= 1'b0;

else if (counter1[15:11] <= duty_cycle1) pwm_out1 <= 1'b1; else pwm_out1 <= 1'b0; end

always @(posedge clk or negedge rst_n) begin if (rst_n ==1'b0) pwm_out2 <= 1'b0;

else if (counter2[14:10] <= duty_cycle2) pwm_out2 <= 1'b1;

本科毕业设计

else pwm_out2 <= 1'b0; end

assign pwm1 = pwm_out1; assign pwm2 = pwm_out2; endmodule

第 42 页 共 42 页

附录B