FPGA可编程逻辑器件芯片EP1S30F780C5N中文规格书 - 图文 

Table5–35.Timing Measurement Methodology for Input Pins(Part 2 of2)

I/O Standard

1.8-V HSTL Class II1.5-V HSTL Class I1.5-V HSTL Class II1.2-V HSTL with OCTDifferential SSTL-2 Class IDifferential SSTL-2 Class IIDifferential SSTL-18 Class IDifferential SSTL-18 Class II1.5-V Differential HSTL Class I1.5-V Differential HSTL Class II1.8-V Differential HSTL Class I1.8-V Differential HSTL Class IILVS

HyperTransportLVPECL

Notes to Table5–35:(1)(2)(3)(4)(5)(6)

Notes(1)–(4)

Measurement Point

VMEAS (V)

0.830.68750.68750.5701.16251.16250.830.830.68750.68750.830.831.16251.16251.5675

Measurement ConditionsVCCIO (V)

1.6601.3751.3751.1402.3252.3251.6601.6601.3751.3751.6601.6602.3252.3253.135

VREF (V)

0.8300.6880.6880.5701.1631.1630.8300.8300.6880.6880.8300.830

Edge Rate (ns)

1.6601.3751.3751.1402.3252.3251.6601.6601.3751.3751.6601.6600.1000.4000.100

Input buffer sees no load at buffer input.

Input measuring point at buffer input is 0.5 ? VCCIO.Output measuring point is 0.5 ? VCC at internal node.Input edge rate is 1 V/ns.

Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV rippleVCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V

Performance

Table5–36 shows StratixII performance for some common designs. All performance values were obtained with the QuartusII software

compilation of library of parameterized modules (LPM), or MegaCore? functions for the finite impulse response (FIR) and fast Fourier transform (FFT) designs.

Stratix II Device Handbook, Volume 1

Timing Model

Stratix II Device Handbook, Volume 1

DC & Switching Characteristics

Table5–36.StratixII Performance Notes(Part 2 of6)

Resources Used

Applications

Note(1)

Performance

-3Speed Grade (2)

349.65420.16349.65354.60420.16349.65364.96420.16359.71364.96420.16359.71364.96420.16359.71

ALUTs

TriMatrix

DSP

Memory

Blocks

Blocks

111111111111111

000000000000000

-3Speed Grade (3)

333.33400.00333.33337.83400.00333.33347.22400.00342.46347.22400.0342.46347.22400.0342.46

-4Speed Grade

303.95364.96303.95307.69364.96303.95317.46364.96313.47317.46364.96313.47317.46364.96313.47

-5SpeedGrade

261.09313.47261.09263.85313.47261.09271.73313.47268.09271.73313.47268.09271.73313.47268.09

Unit

TriMatrix Memory M-RAMblock

Single port

RAM 4K × 144 bit Simple dual-port RAM 4K × 144 bit True dual-port RAM 4K × 144 bitSingle port

RAM 8K × 72 bit Simple dual-port RAM 8K × 72 bit True dual-portRAM 8K × 72 bit Single port

RAM 16K × 36 bitSimple dual-portRAM 16K × 36 bit True dual-port RAM 16K × 36 bitSingle port

RAM 32K × 18 bit Simple dual-port RAM 32K × 18 bit True dual-port RAM 32K × 18 bitSingle port

RAM 64K × 9 bit Simple dual-port RAM 64K × 9 bit True dual-port RAM 64K × 9 bit

000000000000000

MHzMHzMHzMHzMHzMHzMHzMHzMHzMHzMHzMHzMHzMHzMHz

Stratix II Device Handbook, Volume 1

Timing Model

Stratix II Device Handbook, Volume 1

DC & Switching Characteristics

Table5–39.DSP Block Internal Timing Microparameters(Part 2 of2)

-3 SpeedGrade (1)Min (3)

1,1901,190

SymbolParameter

-3 SpeedGrade (2)Min (3)

Max

-4 SpeedGradeMin (4)

Max

-5 SpeedGradeMin (3)

Max

Unit

Max

tCLKL tCLKH

Notes to Table5–39:(1)(2)(3)(4)

Minimum clock low time

Minimum clock high time

1,249 1,249 1,3681,368 1,3681,368

1,594 1,594ps ps These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.

For the -3 and -5 speed grades, the minimum timing is for the commercial temperature grade. Only -4 speed grade devices offer the industrial temperature grade.

For the -4 speed grade, the first number is the minimum timing parameter for industrial devices. The second number is the minimum timing parameter for commercial devices.

Table5–40.M512 Block Internal Timing Microparameters(Part 1 of2)

-3 SpeedGrade (2)Min (4)

Max

-3 SpeedGrade (3)Min (4)

Max

2.433

Note(1)-4 SpeedGradeMin (5)

Max

-5 SpeedGradeMin (4)

2,089

SymbolParameterUnit

Max

3,104

ps

tM512RCtM512WERESUtM512WEREHtM512DATASUtM512DATAH

Synchronous read cycle 2,089time

Write or read enable setup time before clockWrite or read enable hold time after clockData setup time before clock

Data hold time after clock

22203222032220322203

2,3182,089 23 213 23 213 23 213 23 2131,9892,6642,089

2525 233233 2525 233233 2525 233233 2525 233233

29 272 29 272 29 272 29 272 ps ps ps ps ps ps ps ps

tM512WADDRSUWrite address setup

time before clocktM512WADDRHtM512RADDRSUtM512RADDRH

Write address hold time after clock

Read address setup time before clockRead address hold time after clock

Stratix II Device Handbook, Volume 1