EDA课后答案(适用于朱正伟《EDA技术及应用》)

时表决不通过。 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY VOTE7 IS

PORT (MEN:IN STD_LOGIC_VECTOR(6 DOWNTO 0); OUTPUT: OUT BIT); END VOTE7;

ARCHITECTURE BEHAVE OF VOTE7 IS BEGIN

PROCESS(MEN)

VARIABLE TEMP: INTEGER RANGE 0 TO 7; BEGIN TEMP:=0;

FOR I IN 0 TO 6 LOOP IF(MEN(I)='1')THEN TEMP:=TEMP+1; ELSE

TEMP:=TEMP; END IF; END LOOP; CASE TEMP IS

WHEN 0 TO 3 =>OUTPUT<='0'; WHEN 4 TO 7 =>OUTPUT<='1'; END CASE ; END PROCESS; END BEHAVE;

4-7给出1位全减器的VHDL描述,要求:首先设计1位半减器,然后用例化语句将它们连接起来。设X为被减数，Y为减数，DIFF是输出差(DIFF=X-Y),SUB_OUT是借位输出(SUB_OUT=1,X

(1.1)：实现1位半减器H_SUBER(DIFF=X-Y；S_OUT=1,X

PORT( X,Y: IN STD_LOGIC; DIFF,S_OUT: OUT STD_LOGIC); END ENTITY H_SUBER;

ARCHITECTURE HS1 OF H_SUBER IS BEGIN

DIFF <= X XOR (NOT Y); S_OUT <= (NOT X) AND Y;

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END ARCHITECTURE HS1;

--解(1.2)：采用例化实现图4-20的1位全减器

LIBRARY IEEE; --1位二进制全减器顺层设计描述 USE IEEE.STD_LOGIC_1164.ALL; ENTITY F_SUBER IS

PORT(XIN,YIN,SUB_IN: IN STD_LOGIC; SUB_OUT,DIFF_OUT: OUT STD_LOGIC); END ENTITY F_SUBER;

ARCHITECTURE FS1 OF F_SUBER IS

COMPONENT H_SUBER --调用半减器声明语句 PORT(X, Y: IN STD_LOGIC; DIFF,S_OUT: OUT STD_LOGIC); END COMPONENT;

SIGNAL A,B,C: STD_LOGIC; --定义1个信号作为内部的连接线。 BEGIN

U1:H_SUBER PORT MAP(X=>XIN,Y=>YIN, DIFF=>A, S_OUT=>B); U2:H_SUBER PORT MAP(X=>A, Y=>SUB_IN, DIFF=>DIFF_OUT,S_OUT=>C); SUB_OUT <= C OR B; END ARCHITECTURE FS1;

二进制全加器，元件声明与元件例化（COMPONENT,PORT MAP） //或门

LIBRARY IEEE; ；

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY OR2A IS

PORT(A,B : IN STD_LOGIC; C : OUT STD_LOGIC); END OR2A;

ARCHITECTURE ART1 OF OR2A IS BEGIN

C<=A OR B; END ART1;

//半加器；

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY H_ADDER IS

PORT(A,B : IN STD_LOGIC; CO,SO: OUT STD_LOGIC); END H_ADDER;

ARCHITECTURE ART2 OF H_ADDER IS BEGIN

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SO <= A XOR B; CO <= A AND B; END ART2;

1位二进制全加器顶层设计： LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164。ALL;

ENTITY F_ADDER IS

PORT(AIN,BIN,CIN : IN STD_LOGIC; COUT,SUM : OUT STD_LOGIC); END F_ADDER;

ARCHITECTURE ART3 OF F_ADDER IS

COMPONENT H_ADDER //元件声明； PORT(A,B : IN STD_LOGIC; CO,SO: OUT STD_LOGIC); END COMPONENT; COMPONENT OR2A

PORT(A,B : IN STD_LOGIC; C : OUT STD_LOGIC); END COMPONENT;

SIGNAL D,E,F : STD_LOGIC; BEGIN

U1:H_ADDER PORT MAP(AIN,BIN,D,E); //元件例化； U2:H_ADDER PORT MAP(A=>E,B=>CIN,CO=>F,SO=>SUM); U3:OR2A PORT MAP(D,F,COUT); END ART3;

10进制异步复位计数器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY CNT_10_2 IS PORT(

CLK,CLR : IN STD_LOGIC; COUNT : OUT STD_LOGIC ); END;

ARCHITECTURE A OF CNT_10_2 IS

SIGNAL CNT_10 : INTEGER RANGE 0 TO 10; BEGIN

PROCESS(CLK,CLR) BEGIN

IF CLR='1' THEN CNT_10<=0;

ELSIF CLK'EVENT AND CLK='1' THEN CNT_10<=CNT_10+1; IF CNT_10=9 THEN CNT_10<=0;

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COUNT<='1'; ELSE

COUNT<='0'; END IF; END IF; END PROCESS; END A;

10进制异步复位可调占空比

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY CNT_10_1 IS PORT(

CLK,CLR : IN STD_LOGIC; COUNT : OUT STD_LOGIC ); END;

ARCHITECTURE A OF CNT_10_1 IS BEGIN

PROCESS(CLK,CLR)

VARIABLE CNT_10 : INTEGER RANGE 0 TO 10; BEGIN

IF CLR='1' THEN CNT_10:=0;

ELSIF CLK'EVENT AND CLK='1' THEN CNT_10:=CNT_10+1; IF CNT_10=10 THEN CNT_10:=0; COUNT<='1'; ELSE

COUNT<='0'; END IF; END IF; END PROCESS; END A;

10进制同步复位计数器（用信号）

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY CNT_10_2 IS PORT(

A : IN INTEGER RANGE 0 TO 10; CLK,CLR,PST : IN STD_LOGIC; COUNT : OUT STD_LOGIC ); END;

ARCHITECTURE A OF CNT_10_2 IS

SIGNAL CNT_10: INTEGER RANGE 0 TO 9; BEGIN

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