Chapter 1:VC707 Evaluation Board Features
The VC707 board uses power regulators and PMBus compliant digital PWM system controllers from Texas Instruments to supply the core and auxiliary voltages listed in Table1-29.
Table 1-29:
Onboard Power System Devices
ReferenceDesignator
Description
Power RailNet Name
Power RailVoltage
SchematicPage
Device Type
Core voltage controller and regulatorsUCD9248PFC(1)PTD08A020WPTD08D210W(VOUT A)PTD08D210W(VOUT B)PTD08A010W
U42U25
PMBus Controller (Addr=52)Adjustable switching regulator20A, 0.6V to 3.6V
Adjustable switching regulatordual 10A, 0.6Vto 3.6VAdjustable switching regulatordual 10A, 0.6Vto 3.6VAdjustable switching regulator10A, 0.6V to 3.6V
VCCINT_FPGAVCCAUXVCC3V3VCC_ADJ
1.00V1.80V3.30V0-3.30V
4647484849
U20
U12
Auxiliary voltage controller and regulatorsUCD9248PFC(2)PTD08D210W(VOUT A)PTD08D210W(VOUT B)PTD08D210W(VOUT A)PTD08D210W(VOUT B)
U43
PMBus Controller (Addr=53)
Adjustable switching regulatordual 10A, 0.6Vto 3.6VAdjustable switching regulatordual 10A, 0.6Vto 3.6VAdjustable switching regulatordual 10A, 0.6Vto 3.6VAdjustable switching regulatordual 10A, 0.6Vto 3.6V
VCC2V5_FPGAVCC1V5_FPGAMGTAVCCMGTAVTT
2.50V1.50V1.00V1.20V
5051515252
U21
U22
UCD9248PFC(3)PTD08D210W(VOUT A)PTD08D210W(VOUT B)PTD08D210W(VOUT A)PTD08D021W(VOUT B)Linear regulatorsLMZ12002TL1962ADCADP123ADP123
U64
PMBus Controller(Addr=54)
Dual 10A 0.6V - 3.6V Adj. Switching Regulator
VCCAUX_IOVCCBRAMMGTVCCAUXVCCBRAM
2.00V1.00V1.80V1.00V
5354545555
U62
Dual 10A 0.6V - 3.6V Adj. Switching RegulatorDual 10A 0.6V - 3.6V Adj. Switching Regulator
U63
Dual 10A 0.6V - 3.6V Adj. Switching Regulator
U71U62U17U18
Fixed Linear Regulator 2AFixed Linear Regulator, 1.5AFixed Linear Regulator, 300mAFixed Linear Regulator, 300mA
VCC5V0VCC1V8VCC_SPIXADC_VCC
5.00V1.80V2.80V1.80V
46464631
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
Chapter 1:VC707 Evaluation Board Features
Table1-30 defines the voltage and current values for each power rail controlled by the UCD9248 PMBus controller at address 52 (U42).
Table 1-30:
Power Rail Specifications for UCD9248 PMBus Controller at Address 52
Shutdown Threshold(1)
IOUT Over Fault (A)Temp Over Fault (°C)90909090Temp Over Fault (°C)90909090
VOUT Over Fault (V)1.152.073.7952.07
Nominal VOUT (V)PGOff Threshold (V)PGOn Threshold (V)Rise Time (ms)Off Delay (ms)On Delay (ms)RailNumberRailNameSchematicRail Name
1234
Rail #1Rail #2Rail #3Rail #4
VCCINT_FPGAVCCAUXVCC3V3VADJ
11.83.31.8
0.91.622.971.62
0.851.532.8051.53
0000
5555
10543
Fall Time (ms)1111
2010.4110.4110.41
Notes:
1.The values defined in these columns are the voltage, current, and temperature thresholds that cause the regulator to shut down if the value isexceeded.
Table1-31 defines the voltage and current values for each power rail controlled by the UCD9248 PMBus controller at address 53 (U43).
Table 1-31:
Power Rail Specifications for UCD9248 PMBus Controller at Address 53
Shutdown Threshold(1)VOUT Over Fault (V)IOUT Over Fault (A)10.4110.4110.4110.41
Nominal VOUT (V)PGOff Threshold (V)PGOn Threshold (V)Rise Time (ms)Off Delay (ms)On Delay (ms)RailNumberRailNameSchematicRail Name
1234
Rail #1Rail #2Rail #3Rail #4
VCC2V5_FPGAVCC1V5MGTAVCCMGTAVTT
2.51.511.2
2.251.350.91.08
2.1251.2750.851.02
0000
5555
1078
Fall Time (ms)1111
2.8751.7251.451.38
Notes:
1.The values defined in these columns are the voltage, current, and temperature thresholds that causes the regulator to shut down if the value isexceeded.
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
Feature Descriptions
For external measurements an XADC header (J19) is provided. This header can be used to provide analog inputs to the FPGA's dedicated VP/VN channel, and to the VAUXP[0]/VAUXN[0],
VAUXP[8]/VAUXN[8] auxiliary analog input channels. Simultaneous sampling of Channel 0 and Channel 8 is supported.
A user-provided analog signal multiplexer card can be used to sample additional external analog inputs using the 4 GPIO pins available on the XADC header as multiplexer address lines. Figure1-35 shows the XADC header connections.
X-Ref Target - Figure 1-35XADC_VNXADC_VAUX0PXADC_VCC5V0VADJXADC_VAUX8NXADC_DXPXADC_VREFXADC_GPIO_1XADC_GPIO_3135791113151719J192468101214161820XADC_VPXADC_VAUX0NXADC_VAUX8PXADC_DXNXADC_VCC_HEADERXADC_GPIO_0XADC_GPIO_2GNDXADC_AGNDXADC_AGNDUG885_c1_32_030512Figure 1-35:XADC Header (J19)
Table1-33 describes the XADC header J19 pin functions.
Table 1-33:
XADC Header J19 Pinout
J19 PinNumber1, 23, 67, 89, 124, 5, 10111314151619, 20, 17, 18
Description
Dedicated analog input channel for the XADC.
Auxiliary analog input channel 0. Also supports use as I/O inputs when anti-alias capacitor is not present.
Auxiliary analog input channel 8. Also supports use as I/O inputs when anti-alias capacitor is not present.Access to thermal diode.Analog ground reference.1.25V reference from the board.Filtered 5V supply from board.Analog 1.8V supply for XADC.
VCCO supply for bank which is the source of DIO pins.Digital Ground (board) Reference
Digital I/O. These pins should come from the same bank. These I/Os should not be shared with other functions because they are required to support 3-state operation.
Net NameVN, VPXADC_VAUX0P, NXADC_VAUX8N, P
DXP, DXNXADC_AGNDXADC_VREFXADC_VCC5V0XADC_VCC_HEADER
VADJGND
XADC_GPIO_3, 2, 1, 0
VC707 Evaluation Board
UG885 (v1.8) February 20, 2019
Chapter 1:VC707 Evaluation Board Features
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
Appendix B:VITA 57.1 FMC Connector Pinouts
VC707 Evaluation BoardUG885 (v1.8) February 20, 2019
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