EDA计数器及数码显示实验报告

北华航天工业学院

4、十六进制可逆计数器 ①代码

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY KENI16 IS

PORT( CLK,JJ,E:IN STD_LOGIC;

OL,OH :BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0)); END KENI16;

ARCHITECTURE ABC OF KENI16 IS BEGIN

PROCESS(CLK,JJ,E) BEGIN

IF RISING_EDGE(CLK) THEN IF E='1' THEN IF JJ='1' THEN

IF OL=\ ELSIF OL=\ ELSE OL<=OL+1; END IF;

ELSIF JJ='0' THEN

IF OL=\ ELSIF OL=\ ELSE OL<=OL-1; END IF; END IF; END IF; END IF;

END PROCESS; END ABC; ②仿真结果

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北华航天工业学院

5、六进制计数器 ①代码

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY JINZHI6 IS

PORT( CLK,E :IN STD_LOGIC;

O :BUFFER STD_LOGIC_VECTOR(2 DOWNTO 0)); END JINZHI6;

ARCHITECTURE ABC OF JINZHI6 IS BEGIN

PROCESS(CLK,E) BEGIN

IF RISING_EDGE(CLK) THEN IF E='1' THEN

IF O=\ ELSE O<=O+1; END IF; END IF; END IF;

END PROCESS; END ABC; ②仿真结果

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北华航天工业学院

6、数据选择器 ①代码

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY XUANZE IS

PORT( A,B,C,D,E,F :IN STD_LOGIC_VECTOR(3 DOWNTO 0); I :IN STD_LOGIC_VECTOR(2 DOWNTO 0); O :OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END XUANZE;

ARCHITECTURE ABC OF XUANZE IS BEGIN

PROCESS(I) BEGIN

CASE I IS

WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN OTHERS => NULL; END CASE; END PROCESS; END ABC; ②仿真结果

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北华航天工业学院

7、4-7译码器 ①代码

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY YM_47 IS

PORT( I:IN STD_LOGIC_VECTOR(3 DOWNTO 0); O:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); END YM_47;

ARCHITECTURE ABC OF YM_47 IS BEGIN

WITH I SELECT

O<=\ \ \ \ \ \ \ \ \ \ \ \ \END ABC; ②仿真结果

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