FPGA可编程逻辑器件芯片EP3SL70F484I4中文规格书

5.Native Fixed Point DSP Intel Agilex FPGA IP Core References

UG-20213 | 2021.02.05

Parametercoef_b_5coef_b_6coef_b_7

IP GeneratedParametercoef_a_5coef_a_6coef_a_7

ValueDefault ValueDescriptionThese parameters arenot available in

m27×27 operationalmode.

Related Information????

Maximum Input Data Width for Fixed-point Arithmetic on page 78Maximum Output Data Width for Fixed-point Arithmetic on page 80Configurations for Input, Pipeline, and Output Registers on page 63Native Fixed Point DSP Intel Agilex FPGA IP Signals on page 92

5.5.5. Accumulator/Output Chaining

Table 50.

Accumulator/Output Chaining Tab

IP GeneratedParameterValueDefaultValueDescriptionParameterAccumulatorEnable accumulateportenable_accumulateNoYesNoSelect to enable accumulate port.Only available for the following operationalmodes:?m9×9_sumof4?m18×18_sumof2?m18×18_plus36?m18×18_systolic?m27×27Enable 'accumulate'input registeraccumulate_clkenno_regena0ena1ena2no_regSpecify the clock enable signal foraccumulate input register.Only available for the following operationalmodes:?m9×9_sumof4?m18×18_sumof2?m18×18_plus36?m18×18_systolic?m27×27Refer to Configurations for Input, Pipeline, andOutput Registers on page 63 for moreinformation about clock enable restrictions forinput registers.Enable doubleaccumulatorenable_double_accumNoYesNoSelect to enable the double accumulatorfeature.Only available for the following operationalmodes:?m9×9_sumof4?m18×18_sumof2?m18×18_plus36?m18×18_systolic?m27×27NegateEnable 'negate' portenable_negateNoNoSelect to enable negate port.continued... Send Feedback

5.Native Fixed Point DSP Intel Agilex FPGA IP Core ReferencesUG-20213 | 2021.02.05

ParameterIP GeneratedParameterValueYesDefaultValueDescriptionOnly available for the following operationalmodes:?m18×18_sumof2?m18×18_systolic?m27×27Enable 'negate'input registernegate_clkenno_regena0ena1ena2no_regSpecify the clock enable signal for negateinput register.Only available for the following operationalmodes:?m18×18_sumof2?m18×18_systolic?m27×27Refer to Configurations for Input, Pipeline, andOutput Registers on page 63 for moreinformation about clock enable restrictions forinput registers.LoadconstEnable 'loadconst'portenable_loadconstNoYesNoSelect to enable loadconst port.Only available for the following operationmodes:?m9×9_sumof4?m18×18_sumof2?m18×18_plus36?m18×18_systolic?m27×27no_regSpecify the clock enable signal for loadconstinput register.Only available for the following operationmodes:?m9×9_sumof4?m18×18_sumof2?m18×18_plus36?m18×18_systolic?m27×27Refer to Configurations for Input, Pipeline, andOutput Registers on page 63 for moreinformation about clock enable restrictions forinput registers.Specify the preset constant value.This value can be 2N where N is the presetconstant value.Only available for the following operationmodes:?m9×9_sumof4?m18×18_sumof2?m18×18_plus36?m18×18_systolic?m27×27Enable 'loadconst'input registerload_const_clkenno_regena0ena1ena2N value of presetconstantload_const_value0–630Chainin/ChainoutEnable chainin portuse_chainadderNoYesNoSelect to enable chainin port.Only available for the following operationmodes:continued... Send Feedback