128入128出的tst接线器

通信集成电路实验报告

128入128出的tst接线器

128入128出的tst接线器

T-S-T交换网络是由输入级T接线器（TA）和输出级T接线器（TB），中间接有S型时分接线器组成，

T模块包括16个T8接线器，T输入同样调用了16次，在S接线器在总的模块调用，实现了数据信息的传输。

S接线器将数据放入16个寄存器中，通过输出得到控制。 程序

module c_b(clk,rst,data_in,data_out); input clk,rst; input data_in;

output [7:0] data_out; reg [2:0] num; reg [7:0] data_out; always @(posedge clk) if (rst) begin

data_out=8'b0000_0000; num=3'b000; end else

begin

data_out={data_out[6:0],data_in}; num=num+1; end endmodule

module mux(out,hw0,hw1,hw2,hw3,hw4,hw5,hw6,hw7,sel); output [7:0] out;

input [7:0] hw0,hw1,hw2,hw3,hw4,hw5,hw6,hw7; input [2:0] sel; reg [7:0] out;

always @(hw0 or hw1 or hw2 or hw3 or hw4 or hw5 or hw6 or hw7 or sel) begin

case(sel)

3'b000: out=hw0; 3'b001: out=hw1; 3'b010: out=hw2; 3'b011: out=hw3; 3'b100: out=hw4; 3'b101: out=hw5; 3'b110: out=hw6; 3'b111: out=hw7; endcase

end endmodule

module s_ram ( wr_clk,wr_en,wr_addr,data_in,rd_clk,rd_en,rd_addr,data_out ); input wr_clk,wr_en,rd_clk,rd_en; input [7:0] data_in;

input [7:0] wr_addr,rd_addr; output [7:0] data_out; reg [7:0] data_out; reg [7:0] mem [255:0]; always @(posedge wr_clk) if(wr_en)

mem[wr_addr] <= data_in; always @(posedge rd_clk) if(rd_en)

data_out <= mem[rd_addr]; endmodule

module c_ram ( wr_clk,wr_en,wr_addr,data_in,rd_clk,rd_en,rd_addr,data_out ); input wr_clk,wr_en,rd_clk,rd_en; input [7:0] data_in;

input [7:0] wr_addr,rd_addr; output [7:0] data_out; reg [7:0] data_out; reg [7:0] mem [255:0]; always @(posedge wr_clk) if(wr_en)

mem[wr_addr] <= data_in; always @(posedge rd_clk) if(rd_en)

data_out <= mem[rd_addr]; endmodule

module fenlu(data_in,sel,reg0,reg1,reg2,reg3,reg4,reg5,reg6,reg7); input [7:0] data_in; input [2:0] sel;

output [7:0]reg0,reg1,reg2,reg3,reg4,reg5,reg6,reg7; reg [7:0]reg0,reg1,reg2,reg3,reg4,reg5,reg6,reg7; always @(data_in) case (sel)

3'b000: reg0=data_in; 3'b001: reg1=data_in; 3'b010: reg2=data_in; 3'b011: reg3=data_in; 3'b100: reg4=data_in; 3'b101: reg5=data_in; 3'b110: reg6=data_in;

3'b111: reg7=data_in; endcase endmodule

module yiwei(clk,rst,data_in,data_out); input clk,rst;

input [7:0]data_in; output data_out; reg data;

always @(posedge clk) if(rst) data=0; else

data=data_in[7];

assign data_in={data_in[6:0],1'b0}; assign data_out=data; endmodule

module bit(clk,rst,count_8,count_256); input rst,clk;

output [2:0] count_8; output [7:0] count_256; reg [2:0] count_8; reg [7:0] count_256; always @(posedge clk ) begin

if(rst) begin

count_8 <= 3'b000;

count_256<=8'b0000_0000; end else begin

count_256 <= count_256+1; if(count_256%8==0) count_8 <= count_8 +1; end end endmodule

module

mux_s( hw0,hw1,hw2,hw3,hw4,hw5,hw6,hw7,hw8,hw9,hw10,hw11,hw12,hw13,hw14,hw15,

out0,out1,out2,out3,out4,out5,out6,out7,out8,out9,out10,out11,out12,out13,out14,out15, sel0,sel1, sel2, sel3, sel4, sel5, sel6, sel7,sel8,sel9,sel10,sel11,sel12,sel13,sel14,sel15); output [7:0] out0,out1,out2,out3,out4,out5,out6,out7 ,out8,out9,out10,out11,out12,out13,out14,out15;