128入128出的tst接线器

s_ram srom7(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out7), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou7));

s_ram srom8(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out8), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou8));

s_ram srom9(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out9), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou9));

s_ram srom10(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out10), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou10));

s_ram srom11(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out11), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou11));

s_ram srom12(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out12), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou12));

s_ram srom13(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out13), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou13));

s_ram srom14(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out14), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou14));

s_ram srom15(.wr_clk(clk),.wr_en(wr_en),.wr_addr(count_256),.data_in(out15), .rd_clk(clk),.rd_en(rd_en),.rd_addr(data_out),.data_out(ou15)); c_ram_s

css(.wr_clk(clk),.wr_en(wr_en),.wr_addr(wr_addr_s),.data_in(data),.rd_clk(clk),.rd_en(rd_en),.rd_addr(count_256),.data_out(data_out)); t8_out

to0(.data_in(ou0),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7(hwo7)); t8_out

to1(.data_in(ou1),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7(hwo7)); t8_out

to2(.data_in(ou2),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7(hwo7)); t8_out

to3(.data_in(ou3),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7(hwo7)); t8_out

to4(.data_in(ou4),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7(hwo7)); t8_out

to5(.data_in(ou5),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7

(hwo7)); t8_out

to6(.data_in(ou6),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7(hwo7)); t8_out

to7(.data_in(ou7),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7(hwo7)); t8_out

to8(.data_in(ou8),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7(hwo7)); t8_out

to9(.data_in(ou9),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7(hwo7)); t8_out

to10(.data_in(ou10),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7(hwo7)); t8_out

to11(.data_in(ou11),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7(hwo7)); t8_out

to12(.data_in(ou12),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7(hwo7)); t8_out

to13(.data_in(ou13),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7(hwo7)); t8_out

to14(.data_in(ou14),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7(hwo7)); t8_out

to15(.data_in(ou15),.clk(clk),.rst(rst),.wr(wr),.wr_addr(wr_addr),.wr_en(wr_en),.rd_en(rd_en),.hwo0(hwo0),.hwo1(hwo1),.hwo2(hwo2),.hwo3(hwo3),.hwo4(hwo4),.hwo5(hwo5),.hwo6(hwo6),.hwo7(hwo7));

bit bi1(.clk(clk),.rst(rst),.count_8(count_8),.count_256(count_256)); endmodule 验证程序

module tst_tbb; reg data_in;

reg clk,rst,wr,wr_en,rd_en; reg [7:0]wr_addr,wr_addr_s; reg [7:0]data; tst

ttt(data_in,clk,rst,wr,wr_addr,wr_addr_s,wr_en,rd_en,data,hwo0,hwo1,hwo2,hwo3,hwo4,hwo5,hwo6,hwo7);

always #2 clk=~clk; initial begin clk=0; data_in=1;

#2 wr=1;#4 wr_addr=0;wr_addr_s=0; data=1;#4 wr_addr=1;wr_addr_s=1;data=2; #4 wr_addr=2;data=3;#4 wr_addr=3;data=4; #4 wr_addr=4;data=5;#4 wr_addr=5;data=6; #2 wr=0; #4 rst=1; #4 rst=0; #2 wr_en=1; rd_en=1;

#200 data_in=0; #400 $stop; end

endmodule 仿真结果

对本设计的输入接的是同一个信号，方便了设计的编写，对于hwo0的输出为1，说明tst接线器基本能实现信息的传输。