SII51005-4.4
Operating Conditions
Stratix?II devices are offered in both commercial and industrial grades. Industrial devices are offered in -4 speed grades and commercial devices are offered in -3 (fastest), -4, -5 speed grades.
Tables5–1 through 5–32 provide information about absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for StratixII devices.
Absolute Maximum Ratings
Table5–1 contains the absolute maximum ratings for the StratixII device family.
Table5–1.StratixII Device Absolute Maximum RatingsSymbol
VCCINTVCCIOVCCPDVCCAVCCDVIIOUTTSTGTJ(1)(2)(3)(4)
Notes(1), (2), (3)
Minimum
–0.5–0.5–0.5–0.5–0.5–0.5–25
Parameter
Supply voltageSupply voltageSupply voltage
Analog power supply for PLLs
Conditions
With respect to groundWith respect to groundWith respect to groundWith respect to ground
Maximum
1.84.64.61.81.84.640150125
Unit
VVVVVVmA°C°C
Digital power supply for PLLsWith respect to groundDC input voltage (4)DC output current, per pinStorage temperatureJunction temperature
No bias
BGA packages under bias
–65–55
Notes to Tables5–1
See the Operating Requirements for Altera Devices Data Sheet.
Conditions beyond those listed in Table5–1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum ratings for extended periods of time may have adverse affects on the device.Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
During transitions, the inputs may overshoot to the voltage shown in Table5–2 based upon the input duty cycle. The DC case is equivalent to 100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100mA and periods shorter than 20ns.
TriMatrix Embedded Memory Blocks in StratixII and StratixIIGX Devices
Figure2–14.StratixII and Stratix II GX Input/Output Clock Mode in Simple Dual-Port Mode
6 LAB Row Clocks6data[ ]DQENA Memory Block256 ′ 16Data In512 ′ 81,024 ′ 42,048 ′ 24,096 ′ 1Read AddressNote(1)
rdaddress[ ]DQENAData Outbyteena[ ]DQENAByte EnableDQENATo MultiTrackInterconnect (3)wraddress[ ]DQENAWrite Addressrd_addressstallRead AddressClock Enablewr_addressstallWrite AddressClock Enablerden(2)DQENAwrenWrite EnableoutclockenRead EnableinclockeninclockDQENAWritePulseGeneratoroutclockNotes to Figure2–14:(1)(2)(3)
Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This applies to both read and write operations.
The read enable rden signal is not available in the M-RAM block. An M-RAM block in simple dual-port mode is always reading out the data stored at the current read address location.
Refer to the StratixII Device Family Data Sheet (volume 1) of the StratixII Device Handbook or the StratixIIGX Device Family Data Sheet (volume 1) of the StratixIIGX Device Handbook for more information on the MultiTrack? interconnect.
Stratix II Device Handbook, Volume 2
Clock Modes
Figure2–15.StratixII and Stratix II GX Input/Output Clock Mode in Single-Port Mode
6 LAB Row Clocks6data[ ]DQENA Memory Block256 ′ 16Data In512 ′ 81,024 ′ 42,048 ′ 24,096 ′ 1AddressNote(1)
address[ ]DQENAData Outbyteena[ ]DQENAByte EnableDQENATo MultiTrackInterconnect (2)addressstallAddressClock EnablewrenoutclockenWrite EnableinclockeninclockDQENAWritePulseGeneratoroutclockNotes to Figure2–15:(1)(2)
Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This applies to both read and write operations.
Refer to the StratixII Device Family Data Sheet (volume 1) of the StratixII Device Handbook or the StratixIIGX Device Family Data Sheet (volume 1) of the StratixIIGX Device Handbook for more information on the MultiTrack interconnect.
Read/Write Clock Mode
StratixII and StratixIIGX TriMatrix memory blocks can implement read/write clock mode for simple dual-port memory. This mode uses up to two clocks. The write clock controls the blocks’ data inputs, write address, and write enable signals. The read clock controls the data output, read address, and read enable signals. The memory blocks support independent clock enables for each clock for the read- and write-side registers. Asynchronous clear signals for the registers, however, are not supported. Figure2–16 shows a memory block in read/write clock mode.
Stratix II Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in StratixII and StratixIIGX Devices
Figure2–16.StratixII and StratixIIGX Read/Write Clock Mode
6 LAB Row Clocks6data[ ]DQENANote(1)
Memory Block256 ′ 16Data In512 ′ 81,024 ′ 42,048 ′ 24,096 ′ 1Read Addressrdaddress[ ]DQENAData Outbyteena[ ]DQENAByte EnableDQENATo MultiTrackInterconnect (3)wraddress[ ]DQENAWrite Addressrd_addressstallRead AddressClock Enablewr_addressstallWrite AddressClock Enablerden(2)DQENAwrenWrite EnablerdclockenRead EnablewrclockenwrclockDQENAWritePulseGeneratorrdclockNotes to Figure2–16:(1)(2)(3)
Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This applies to both read and write operations.
The read enable rden signal is not available in the M-RAM block. An M-RAM block in simple dual-port mode is always reading the data stored at the current read address location.
Refer to the StratixII Device Family Data Sheet (volume 1) of the StratixII Device Handbook or the StratixIIGX Device Family Data Sheet (volume 1) of the StratixIIGX Device Handbook for more information on the MultiTrack interconnect.
Stratix II Device Handbook, Volume 2
TriMatrix Embedded Memory Blocks in StratixII and StratixIIGX Devices
Stratix II Device Handbook, Volume 2
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