Feature Descriptions
ProcessingSystem(PS)MemoryInterfacesProgrammableLogic(PL)Input OutputPeripherals(IOP)High-BandwidthAMBA? AXI InterfacesApplicationProcessor Unit (APU)InterconnectCommonPeripheralsCustomPeripheralsCommon AcceleratorsCustom AcceleratorsUG954_c1_03_100112ZC706 Evaluation Board User GuideUG954 (v1.8) August 6, 2019
Feature Descriptions
The connections between the USB Micro-B connector at J2 and the PHY at U12 are listed in Table1-8.
Table 1-8:
USB Connector Pin Assignments and Signal Definitions Between J2 and U12
Net Name
USB_VBUS_SELUSB_D_NUSB_D_PGND
USB Connector
J1Pin
1235
Description
+5V from host system
Bidirectional differential serial data (N-side)Bidirectional differential serial data (P-side)Signal ground
Name
VBUSD_ND_PGND
USB3320 (U12)
Pin
22191833
The connections between the USB 2.0 PHY at U12 and the XC7Z045 SoC are listed in Table1-9.
Table 1-9:
USB 2.0 ULPI Transceiver Connections to the XC7Z045 SoC
XC7Z045 (U1)
Pin Name
PS_MIO36PS_MIO31PS_MIO32PS_MIO33PS_MIO34PS_MIO35PS_MIO28PS_MIO37PS_MIO38PS_MIO39PS_MIO30PS_MIO29PS_MIO7
Bank
501501501501501501501501501501501501500
Pin Number
H17H21K17G22K18G21L17B21A20F18L18E8D5
Schematic Net Name
USB_CLKOUTUSB_NXTUSB_DATA0USB_DATA1USB_DATA2USB_DATA3USB_DATA4USB_DATA5USB_DATA6USB_DATA7USB_STPUSB_DIRUSB_RESET_B_AND
USB3320 (U12) Pin
1234567910132931
27 (via AND gate U13)
For additional information on the Zynq-7000 SoC device USB controllers, see Zynq-7000 SoC Overview (DS190) and Zynq-7000 SoC Technical Reference Manual (UG585).
ZC706 Evaluation Board User GuideUG954 (v1.8) August 6, 2019
Feature Descriptions
Table 1-19:
U51 Pin
Board Connections for PHY Configuration Pins
Setting
VCCP1V8PHY_LED0GNDPHY_LED0VCCP1V8GNDPHY_LED0PHY_LED1VCCP1V8
Configuration
PHYAD[1]=1PHYAD[3]=0ENA_XC=0ENA_XC=0ENA_XC=1RGMII_TX=0RGMII_TX=0RGMII_TX=1RGMII_TX=1
PHYAD[0]=1PHYAD[2]=1PHYAD[4]=0PHYAD[4]=1PHYAD[4]=1RGMII_RX=0RGMII_RX=1RGMII_RX=0RGMII_RX=1
CONFIG (64)CONFIG1 (1)CONFIG2 (2)
CONFIG3 (3)
The Ethernet connections from the XC7Z045 SoC at U1 to the 88E1116R PHY device at U51 are listed in Table1-20.Table 1-20:
Ethernet Connections, XC7Z045 SoC to the PHY DeviceXC7Z045 (U1) Pin
Pin Name
PS_MIO53PS_MIO52PS_MIO16PS_MIO21PS_MIO20PS_MIO19PS_MIO18PS_MIO17PS_MIO22PS_MIO27PS_MIO26PS_MIO25PS_MIO24PS_MIO23
Bank
501501501501501501501501501501501501501501
PinNumber
C18D19L19J19M20J20K20K21L20G20M17G19M19J21
SchematicNet Name
PHY_MDIOPHY_MDCPHY_TX_CLKPHY_TX_CTRLPHY_TXD3PHY_TXD2PHY_TXD1PHY_TXD0PHY_RX_CLKPHY_RX_CTRLPHY_RXD3PHY_RXD2PHY_RXD1PHY_RXD0
M88E1116R PHY U51Pin
4548606362615958534955545150
Name
MDIOMDCTX_CLKTX_CTRLTXD3TXD2TXD1TXD0RX_CLKRX_CTRLRXD3RXD2RXD1RXD0
Ethernet PHY Clock Source
A 25.00 MHz 50 ppm crystal at X1 is the clock source for the 881116R PHY at U51. Figure1-21 shows the clock source.
ZC706 Evaluation Board User GuideUG954 (v1.8) August 6, 2019
Feature Descriptions
ZC706 Evaluation Board User GuideUG954 (v1.8) August 6, 2019
Feature Descriptions
Table 1-21:Pin
1235
USB Connector J21 Pin Assignments and Signal DefinitionsName
Net Name
USB_UART_VBUSUSB_UART_D_NUSB_UART_D_PUSB_UART_GND
USB Connector (J21)
Description
+5V VBUS Powered
Bidirectional differential serial data (N-side)Bidirectional differential serial data (P-side)Signal ground
CP2103GM (U52)Pin
7843229
Name
REGINVBUSD–D+GND1CNR_GND
VBUSD_ND_PGND
XC7045 SoC (U1)
Pin NameBankPIN
PS_MIO48PS_MIO49
501501
C19D18
TXRX
Schematic Net CP2103GM Device (U52)
NameFunctionDirectionIOSTANDARDPINFunctionDirection
OutputInput
LVCMOS18LVCMOS18
USB_UART_RXUSB_UART_TX
2425
RXDTXD
InputOutput
ZC706 Evaluation Board User Guide
UG954 (v1.8) August 6, 2019
相关推荐：
loading