2.5-V, or 3.3-V power supply, depending on the output requirements. Theoutput levels are compatible with systems of the same voltage as the power supply (for example, when VCCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems). When VCCIO pins are connected to a 3.3-V power supply, the output high is 3.3V and is compatible with 3.3-V or 5.0-V systems. Table53 summarizes StratixGX MultiVolt I/O support.
Table53.StratixGX MultiVolt I/O Support Note(1)
VCCIO (V)
1.51.82.53.3
Notes to Table53:(1)(2)(3)(4)(5)(6)
To drive inputs higher than VCCIO but less than 4.1 V, disable the PCI clamping diode. However, to drive 5.0-V inputs to the device, enable the PCI clamping diode to prevent VI from rising above 4.0 V.The input pin current may be slightly higher than the typical value.
Although VCCIO specifies the voltage necessary for the StratixGX device to drive out, a receiving device powered at a different level can still interface with the StratixGX device if it has inputs that tolerate the VCCIO value.StratixGX devices can be 5.0-V tolerant with the use of an external resistor and the internal PCI clamp diode.This is the external signal that is driving the StratixGX device.
This represents the system voltage that StratixGX supports when a VCCIO pin is connected to a specific voltage level. For example, when VCCIO is 3.3 V and if the I/O standard is LVTTL/LVCMOS, the output high of the signal coming out from StratixGX is 3.3 V and is compatible with 3.3-V or 5.0-V systems.
Input Signal (5)
1.5 Vvv (2)
1.8 Vvv
2.5 Vv (2)v (2)vv (2)
3.3 Vv (2)v (2)vv
v (4)5.0 V
1.5 Vvv (3)v (3)v (3)
Output Signal (6)1.8 V
2.5 V
3.3 V
5.0 V
vv (3)v (3)
vv (3)
v
v
Power
Sequencing & Hot Socketing
Because StratixGX devices can be used in a mixed-voltage environment, they have been designed specifically to tolerate any possible power-up sequence. Therefore, the VCCIO and VCCINT power supplies may be powered in any order.
Signals can be driven into StratixGX devices before and during power up without damaging the device. In addition, StratixGX devices do not drive out during power up. Once operating conditions are reached and the device is configured, StratixGX devices operate as specified by the user. For more information, see Hot Socketing in the Selectable I/O Standards in Stratix & StratixGX Devices chapter in the Stratix Device Handbook, Volume2.
StratixGX FPGA Family
Table57.StratixGX JTAG Timing Parameters & Values(Part 2 of2)Symbol
tJPHtJPCOtJPZXtJPXZtJSSUtJSHtJSCOtJSZXtJSXZ
Parameter
JTAG port hold timeJTAG port clock to output
JTAG port high impedance to valid outputJTAG port valid output to high impedanceCapture register setup timeCapture register hold timeUpdate register clock to output
Update register high impedance to valid outputUpdate register valid output to high impedance
Min (ns)Max (ns)
45
252525
2045
353535
f
For more information on JTAG, see the following documents:
■■
AN 39: IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices Jam Programming & Test Language Specification
SignalTap
Embedded Logic Analyzer
StratixGX devices feature the SignalTap embedded logic analyzer, which monitors design operation over a period of time through the
IEEEStd.1149.1 (JTAG) circuitry. A designer can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is particularly important for advanced packages, such as FineLine BGA packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured.The logic, circuitry, and interconnects in the StratixGX architecture are configured with CMOS SRAM elements. StratixGX devices are
reconfigurable and are 100% tested prior to shipment. As a result, the designer does not have to generate test vectors for fault coverage
purposes, and can instead focus on simulation and design verification. In addition, the designer does not need to manage inventories of different ASIC designs. StratixGX devices can be configured on the board for the specific functionality required.
StratixGX devices are configured at system power-up with data stored in an Altera serial configuration device or provided by a system controller. Altera offers in-system programmability (ISP)-capable configuration devices that configure StratixGX devices via a serial data stream.
StratixGX devices can be configured in under 100 ms using 8-bit parallel data at 100MHz. The StratixGX device’s optimized interface allows microprocessors to configure it serially or in parallel, and synchronously
Configuration
Configuration
StratixGX FPGA Family
Multiple StratixGX devices can be configured in any of five configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device.Table58.Data Sources for ConfigurationConfiguration Scheme
Configuration devicePassive serial (PS)Passive parallel asynchronous (PPA)Fast passive parallelJTAG
Data Source
Enhanced or EPC2 configuration device
ByteBlasterMV or MasterBlaster download cable or serial data sourceParallel data sourceParallel data source
MasterBlaster or ByteBlasterMV download cable or a microprocessor with a Jam or JBC file (.jam or .jbc)
Partial Reconfiguration
The enhanced PLLs within the StratixGX device family support partial reconfiguration of their multiply, divide, and time delay settings without reconfiguring the entire device. Designers can use either serial data from the logic array or regular I/O pins to program the PLL’s counter settings in a serial chain. This option provides considerable flexibility for
frequency synthesis, allowing real-time variation of the PLL frequency and delay. The rest of the device is functional while reconfiguring the PLL. See “Enhanced PLLs” on page143 for more information on StratixGX PLLs.
Remote Update Configuration Modes
StratixGX devices also support remote configuration using an Altera enhanced configuration device (for example, EPC16, EPC8, and EPC4 devices) with page mode selection. Factory configuration data is stored in the default page of the configuration device. This is the default configuration which contains the design required to control remote updates and handle or recover from errors. The designer writes the
factory configuration once into the flash memory or configuration device. Remote update data can update any of the remaining pages of the
configuration device. If there is an error or corruption in a remote update configuration, the configuration device reverts back to the factory configuration information.
PreliminaryConfiguration
There are two remote configuration modes: remote and local
configuration. Designers can use the remote update configuration mode for all three configuration modes: serial, parallel synchronous, and parallel asynchronous. Configuration devices (for example, EPC16 devices) only support serial and parallel synchronous modes.
Asynchronous parallel mode allows remote updates when an intelligent host is used to configure the StratixGX device. This host must support page mode settings similar to an EPC16 device.
Remote Update Mode
When the StratixGX device is first powered-up in remote update programming mode, it loads the configuration located at page
address000. The factory configuration should always be located at page address000, and should never be remotely updated. The factory configuration contains the required logic to perform the following operations:
■■■
Determine the page address/load location for the next application’sconfiguration data
Recover from a previous configuration error
Receive new configuration data and write it into the configurationdevice
The factory configuration is the default and takes control if an error occurs while loading the application configuration.
While in the factory configuration, the factory-configuration logic performs the following operations:
■■■
Loads a remote update-control register to determine the pageaddress of the new application configuration
Determines whether to enable a user watchdog timer for theapplication configuration
Determines what the watchdog timer setting should be if it isenabled
The user watchdog timer is a counter that must be continually reset within a specific amount of time in the user mode of an application
configuration to ensure that valid configuration occurred during a remote update. Only valid application configurations designed for remote update can reset the user watchdog timer in user mode. If a valid application configuration does not reset the user watchdog timer in a specific amount of time, the timer updates a status register and loads the factory configuration. The user watchdog timer is automatically disabled for factory configurations.
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