FPGA实验报告

end if; end process;

process (Clock)

variable a:std_logic_vector(2 downto 0); begin

if Clock'event and Clock='1' then if Reset='1' then

q<=\ else

if Count=\ Count<=\ else

Count<=Count+1; end if;

a:=Strait_A&Block_A&Turn_A; case a is

when \

when \ when \ when \ when \ when \ when \ when \ when others=> null; end case; when \

when \ when \ when \ when \ when \ when \ when \ when others=> null; end case; when \

when \ when \ when \ when \ when \ when \

when \ when others=> null; end case;

when others=> null; end case; end if; end if;

end process; end traffic;