Y=~(A+B(C+D))版图设计

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附录一电路原理图网表：

* SPICE netlist written by S-Edit Win32 7.03 * Written on Jul 2, 2013 at 23:31:28 * Waveform probing commands *.probe

.include D:\\tanner\\TSpice70\\models\\ml2_125.md .options probefilename=\+ probesdbfile=\+ probetopmodule=\*.param l=0.5u *Vdd Vdd Gnd 5

*.tran/op 10n 800n method=bdf

*.print tran v(A) v(B) v(C) v(D) v(Y)

*va A GND PULSE (0 5 400n 0.1n 0.1n 400n 800n) *vb B GND PULSE (0 5 210n 0.1n 0.1n 200n 400n) *vc C GND PULSE (0 5 90n 0.1n 0.1n 100n 200n) *vd D GND PULSE (0 5 50n 0.1n 0.1n 50n 100n) * Main circuit: Module0

M1 Y B N3 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M2 Gnd D N3 Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M3 N3 C Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M4 Y A Gnd Gnd NMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M5 N1 A Vdd Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M6 N2 C N1 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M7 Y B N1 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u M8 Y D N2 Vdd PMOS L=2u W=22u AD=66p PD=24u AS=66p PS=24u * End of main circuit: Module0

附录二版图网表：

* Circuit Extracted by Tanner Research's L-Edit Version 9.00 / Extract Version 9.00 ;

* TDB File: D:\\tanner\\LIE\\lie.tdb * Cell: Cell0

Version 1.67

* Extract Definition File: ..\\LEdit90\\Samples\\SPR\\example1\\lights.ext * Extract Date and Time: 07/05/2013 - 09:38 .include D:\\tanner\\TSpice70\\models\\ml2_125.md * Warning: Layers with Unassigned AREA Capacitance. *

* * * *

* Warning: Layers with Unassigned FRINGE Capacitance. *

* * * * *

* *

* Warning: Layers with Zero Resistance. * * * * * NODE NAME ALIASES * 1 = C (38,-35)

* 2 = D (30.5,-35) * 3 = B (22,-34.5) * 4 = A (14,-34.5) * 5 = GND (8.5,-18.5) * 6 = Vdd (9.5,37.5) * 7 = Y (58.5,7.5)

*.include D:\\tanner\\TSpice70\\models\\ml2_125.md *.options probefilename=\*+ probesdbfile=\*+ probetopmodule=\*.param l=0.5u *Vdd Vdd Gnd 5

*.tran/op 10n 800n method=bdf

*.print tran v(A) v(B) v(C) v(D) v(Y)

*va A GND PULSE (0 5 400n 0.1n 0.1n 400n 800n) *vb B GND PULSE (0 5 210n 0.1n 0.1n 200n 400n) *vc C GND PULSE (0 5 90n 0.1n 0.1n 100n 200n) *vd D GND PULSE (0 5 50n 0.1n 0.1n 50n 100n) M1 9 C 10 Vdd PMOS L=2u W=6u

* M1 DRAIN GATE SOURCE BULK (38 16 40 22) M2 10 D Y Vdd PMOS L=2u W=6u

* M2 DRAIN GATE SOURCE BULK (30 16 32 22) M3 Y B 9 Vdd PMOS L=2u W=6u

* M3 DRAIN GATE SOURCE BULK (22 16 24 22) M4 9 A Vdd Vdd PMOS L=2u W=6u

* M4 DRAIN GATE SOURCE BULK (14 16 16 22) M5 8 C GND GND NMOS L=2u W=6u

* M5 DRAIN GATE SOURCE BULK (38 -11 40 -5) M6 GND D 8 GND NMOS L=2u W=6u

* M6 DRAIN GATE SOURCE BULK (30 -11 32 -5) M7 8 B Y GND NMOS L=2u W=6u

* M7 DRAIN GATE SOURCE BULK (22 -11 24 -5) M8 Y A GND GND NMOS L=2u W=6u

* M8 DRAIN GATE SOURCE BULK (14 -11 16 -5) * Total Nodes: 10 * Total Elements: 8

* Total Number of Shorted Elements not written to the SPICE file: 0 * Extract Elapsed Time: 0 seconds .END

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