EDA课程设计实验报告

引脚设置。

编译下载。（FPGA下载文件是*.sof）

2.A/D转换电路（FPGA）

程序部分

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY ADCINT IS

PORT(D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); CLK:IN STD_LOGIC; EOC:IN STD_LOGIC; ALE:OUT STD_LOGIC; START:OUT STD_LOGIC; OE:OUT STD_LOGIC; ADDA:OUT STD_LOGIC; LOCK0:OUT STD_LOGIC;

Q:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END ADCINT;

ARCHITECTURE behav OF ADCINT IS

TYPE states IS(st0,st1,st2,st3,st4);

SIGNAL current_state,next_state:states:=st0; SIGNAL REGL :STD_LOGIC_VECTOR(7 DOWNTO 0); SIGNAL LOCK :STD_LOGIC; BEGIN

ADDA<='1';

Q<=REGL; LOCK0<=LOCK;

COM:PROCESS(current_state,EOC) BEGIN

CASE current_state IS

WHEN st0=>ALE<='0';START<='0';LOCK<='0';OE<='0'; next_state<=st1;

WHEN st1=>ALE<='1';START<='1';LOCK<='0';OE<='0'; next_state<=st2;

WHEN st2=>ALE<='0';START<='0';LOCK<='0';OE<='0'; IF(EOC='1')THEN next_state<=st3; ELSE next_state<=st2; END IF;

WHEN st3=>ALE<='0';START<='0';LOCK<='0';OE<='1'; next_state<=st4;

WHEN st4=>ALE<='0';START<='0';LOCK<='1';OE<='1'; next_state<=st0;

WHEN OTHERS=>next_state<=st0; END CASE;

END PROCESS COM; REG:PROCESS(CLK) BEGIN

IF(CLK'EVENT AND CLK='1')THEN current_state<=next_state; END IF;

END PROCESS REG; LATCH1:PROCESS(LOCK) BEGIN

IF LOCK='1' AND LOCK'EVENT THEN REGL<=D; END IF;

END PROCESS LATCH1; END behav;

1）新建设计及工程

打开QuartusⅡ，选择菜单File→New，新建VHDL File文件。

输入程序，选择File→Save As，同时创建工程。