FPGA可编程逻辑器件芯片XCZU27DR-2FFVG1517I中文规格书 - 图文

FFV1759 Flip-Chip Fine-Pitch BGA Package Specifications

(1.00mm Pitch)

X-Ref Target - Figure 4-9Figure 4-9:FFV1759 Flip-Chip Fine-Pitch BGA Package Specification

Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2018

RF1759 Flip-Chip Fine-Pitch BGA Package Specifications (1.00mm Pitch)

RF1759 Flip-Chip Fine-Pitch BGA Package Specifications

(1.00mm Pitch)

X-Ref Target - Figure 4-10Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2018

Chapter 3:Pinout and I/O Bank Diagrams

FF1155 Package—HX255T and HX380T

X-Ref Target - Figure 3-91ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAP12345678910111213141516171819202122232425262728293031323334ABCDEFGHJKRLMRR12NDIYHSSSMCLSSSJBUfEEVAVV0PNPRTUVWYAAABACADAEVVEEVVEKOEVEVVEEVEVAFAGAHAJEVVEEbG2345EEEVVAKALAMANGAPVUser I/O PinsIO_LXXY_#Multi-Function PinsSMVREFVRNVRPP_GCN_GCCCD0 - D31A0 - A25bCSO_BTransceiver PinsEMGTAVCCVMGTAVTTMGTAVTTRCALMGTREFCLKPMGTREFCLKNGMGTRREFMGTRXPMGTRXNMGTTXPV678910111213141516171819202122232425262728293031323334Dedicated PinsCCCLKBCSI_BNDINDDONEADOUT_BUSYHHSWAPENYINIT210M2, M1, M0PPROGRAM_BURDWRKTCKITDIOTDOMTMSJDXPLDXNOther PinsGNDRRSVDfVFSVBATTVCCAUXVCCINTVCCOMGTHAVCCPLLMGTHAVCCRXMGTHAVCCMGTHAVTTMGTHAGNDMGTRBIASFigure 3-9:FF1155 Package—HX255T and HX380T Pinout Diagram

VnNCFFLOATMGTTXNSAVDD, AVSS, VP,VN, VREFP, VREFNUG365_c3_09_111411Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2018

Chapter 3:Pinout and I/O Bank Diagrams

FF1759/RF1759 Package—LX550T and SX475T

X-Ref Target - Figure 3-151ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPARATAUAVAWAYBABB123456V7891011G12V131415161718192021222324252627282930313233343536373839404142ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPARATAUAVAWAYBABBVVVVVVVVVVVEEEEEEEBUCNPDHYVVVVESEEESSLSSSJfVVVVVVVVVVVEEEEEIOEAE201KMb23456789101112131415161718192021222324252627282930313233343536373839404142User I/O PinsIO_LXXY_#Multi-Function PinsSMVREFVRNVRPP_GCN_GCCCD0 - D31A0 - A25bCSO_BTransceiver PinsEMGTAVCCVMGTAVTTMGTAVTTRCALMGTREFCLKPMGTREFCLKNGMGTRREFMGTRXPMGTRXNMGTTXNMGTTXPDedicated PinsCCCLKBCSI_BNDINDDONEADOUT_BUSYHHSWAPENYINIT210M2, M1, M0PPROGRAM_BURDWRKTCKITDIOTDOMTMSJDXPLDXNOther PinsGNDfVFSVBATTVCCAUXVCCINTVCCOnNCFFLOATVSAVDD, AVSS, VP,VN, VREFP, VREFNUG365_c3_15_082709Figure 3-15:FF1759/RF1759 Package—LX550T and SX475T Pinout Diagram

Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2018

Chapter 3:Pinout and I/O Bank Diagrams

FF1923 Package—HX255T

X-Ref Target - Figure 3-211ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMnANAPGARATAUAVAWnAYnBABBBCBD1nn234567891011121314151617181920212223242526272829303132333435363738394041424344ABCDEFGHJKLMNRRRDEEH0ENOESKESSMELSSSJAIEfnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnbnnnnnnnnnnnnnnnnnnnnEnnEnEnEnEnEnEnEGVnnnnnnnECEBEUEY12PEERRRPRTUVVVWYAAVVVABACADAEVVVAFAGAHAJVVVVVVVVnnnnnVnnnnnnn23nnnnnn4n5nnnnnn67nnnnn8nnnnn9nnnnnnnnnnnnnnnnnnnnnnAKALnnnnVnnnVnnAMANnAPARnnnnVnnVnnnVnnATAUnnnAVAWnnnnnnnnnVnnVnnnVnnAYBAnnnBBBCBDnn1011121314151617181920212223242526272829303132333435363738394041424344User I/O PinsIO_LXXY_#Multi-Function PinsSMVREFVRNVRPP_GCN_GCCCD0 - D31A0 - A25bCSO_BTransceiver PinsEMGTAVCCVMGTAVTTMGTAVTTRCALMGTREFCLKPMGTREFCLKNGMGTRREFMGTRXPMGTRXNMGTTXPDedicated PinsCCCLKBCSI_BNDINDDONEADOUT_BUSYHHSWAPENYINIT210M2, M1, M0PPROGRAM_BURDWRKTCKITDIOTDOMTMSJDXPLDXNOther PinsGNDRRSVDfVFSVBATTVCCAUXVCCINTVCCOMGTHAVCCPLLMGTHAVCCRXMGTHAVCCMGTHAVTTMGTHAGNDMGTRBIASFigure 3-21:FF1923 Package—HX255T Pinout Diagram

VnNCFFLOATMGTTXNSAVDD, AVSS, VP,VN, VREFP, VREFNUG365_c3_21_111411Virtex-6 FPGA PackagingUG365 (v2.6) October 3, 2018