电子电路 L6- Latches, the D Flip-Flop and Counter Design - 图文 

Latches, the D Flip-Flop & Counter DesignECE 152A –Winter 2012Reading Assignment?Brown and Vranesic?7Flip-Flops, Registers, Counters and a Simple Processor??7.1 Basic Latch7.2 Gated SR Latch?7.2.1 Gated SR Latch with NAND Gates7.3.1 Effects of Propagation Delays?7.3 Gated D Latch?February 6, 2012ECE 152A -Digital Design Principles2Reading Assignment?Brown and Vranesic(cont)?7Flip-Flops, Registers, Counters and a Simple Processor (cont)?7.4 Master-Slave and Edge-Triggered D Flip-Flops????7.4.1 Master-Slave D Flip-Flop7.4.2 Edge-Triggered D Flip-Flop7.4.3 D Flip-Flop with Clear and Preset7.4.4 Flip-Flop Timing Parameters (2ndedition)February 6, 2012ECE 152A -Digital Design Principles3Reading Assignment?Roth?11 Latches and Flip-Flops????11.1 Introduction11.2 Set-Reset Latch11.3 Gated D Latch11.4 Edge-Triggered D Flip-FlopFebruary 6, 2012ECE 152A -Digital Design Principles4Reading Assignment?Roth(cont)?12 Registers and Counters????12.1 Registers and Register Transfers12.2 Shift Registers12.3 Design of Binary Counters12.4 Counters for Other SequencesFebruary 6, 2012ECE 152A -Digital Design Principles5