Chapter 2: XPHY Architecture
Table 19: Register Description (BS_RESET_CTRL) (cont'd)
BS_RESET_CTRL
Bits
[1]
ADDR: 0x03
Name
bs_reset
AccessType
rw
Reset Value
0x0
Description
NIBBLESLICE reset. When set, NIBBLESLICEs notmasked by BS_RST_MASK.bs_reset_mask arereset. Prior to asserting this bit, set PHY_WRENand PHY_RDEN to 0 if they are not already tiedoff to 0, regardless of the value of the TX_GATINGor RX_GATING attributes. The bs_reset must beasserted for a minimum amount of time, definedby its data width (the TX_DATA_WIDTH andRX_DATA_WIDTH attributes):
For data width of 8: 1 CTRL_CLK cycle + 72PLL_CLK cycles
For data width of 4: 1 CTRL_CLK cycle + 40PLL_CLK cycles
For data width of 2: 1 CTRL_CLK cycle + 24PLL_CLK cycles
?
??
While bs_reset is asserted, the TX IOBs ofNIBBLESLICEs not masked by
BS_RST_MASK.bs_reset_mask are set to the valueof the their associated TX_INIT_# attribute. Afterbs_reset is deasserted, data can be transmittedimmediately. For receivers, however, the firstFIFO_EMPTY deassertion should be used to knowwhen receiving valid data. Also, after thedeassertion of bs_reset, PHY_RDEN andPHY_WREN can now be changed from 0.
[2]
rw
0x0
bs_reset_tri
Tristate NIBBLESLICE reset. When asserted, thetristate NIBBLESLICE is set to the value of theTX_INIT_TRI attribute if not masked by
BS_RST_MASK.bs_reset_tri_mask. bs_reset_trimust be asserted for a minimum amount oftime, defined by the interface's data width (theTX_DATA_WIDTH and RX_DATA_WIDTHattributes):
?
??
[15:3]
RESERVED
For data width of 8: 1 CTRL_CLK cycle + 72PLL_CLK cycles
For data width of 4: 1 CTRL_CLK cycle + 40PLL_CLK cycles
For data width of 2: 1 CTRL_CLK cycle + 24PLL_CLK cycles
Set PHY_WREN = 0 when issuing this reset.Reserved.
Table 20: Register Description (PQTR)
PQTR
Bits
[8:0][12:9]
ADDR: 0x07
Name
pqtr_dly
AccessType
rw
Reset Value
0x0
RESERVED
Description
P-clk quarter delay. See pqtr_crse for thedifferent ways to update pqtr_dly.Reserved.
AM010 (v1.2) April 2, 2021
Versal ACAP SelectIO Resources Architecture Manual
Chapter 2: XPHY Architecture
Table 20: Register Description (PQTR) (cont'd)
PQTR
Bits
[13]
ADDR: 0x07
Name
pqtr_crse
AccessType
wo
Reset Value
0x0
Description
Along with pqtr_dec and pqtr_inc, determineshow pqtr_dly will change.
{pqtr_inc, pqtr_dec, pqtr_crse}:
000, 001, 110, 111: This allows for pqtr_dly tobe written to directly.
100: Increment pqtr_dly by one tap. Wraparound to 0x0 will happen when thisincrement occurs at pqtr_dly = 0x1ff.010: Decrement pqtr_dly by one tap. Wraparound to 0x1ff will happen when thisdecrement occurs at pqtr_dly = 0x0.101: Increment pqtr_dly by
INCDEC_CRSE.incdec_crse. When pqtr_dly isclose to 0x1ff, this increment may wrap itaround to above 0x0.
011: Decrement pqtr_dly by
INCDEC_CRSE.incdec_crse. When pqtr_dly isclose to 0x0, this decrement may wrap itaround to below 0x1ff.
To prevent misalignment, if the update is bymore than one tap, wait five CTRL_CLK + four
strobe/capture clock cycles, then apply a bs_reseton all NIBBLESLICEs affected by the quarterdelay line update (even if it's through inter-nibble or inter-byte clocking) after the update.
[14][15]
wowo
0x00x0
pqtr_decpqtr_inc
P-clk quarter delay decrement. See thedescription for pqtr_crse.
P-clk quarter delay increment. See thedescription for pqtr_crse.
Table 21: Register Description (NQTR)
NQTR
Bits
[8:0][12:9]
ADDR: 0x08
Name
nqtr_dly
AccessType
rw
Reset Value
0x0
RESERVED
Description
N-clk quarter delay. See nqtr_crse for thedifferent ways to update nqtr_dly.Reserved.
AM010 (v1.2) April 2, 2021
Versal ACAP SelectIO Resources Architecture Manual
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