Reset
X-Ref Target - Figure 5-9GTXRESETInternal TXRESETInternal RXRESET~120 μsInternal RXBUFRESETUG198_c5_09_120707Figure 5-9:Reset Sequence Triggered by the GTXRESET Pulse
The following GTX_DUAL sections are affected by the GTXRESET sequence:?????
Shared PMA PLL
GTX0 transmit section (PMA and PCS)GTX0 receive section (PMA and PCS)GTX1 transmit section (PMA and PCS)GTX1 receive section (PMA and PCS)
GTX Component-Level Resets
Component resets are primarily used for special cases. These resets are needed when only the reset of a specific GTX_DUAL subsection is required. Each of the component-level reset signals is described in Table5-6, page102.
All component resets are asynchronous with the exception of PRBSCNTRESET, which is synchronous to RXUSRCLK2.
Link Idle Reset Support
The Link Idle Reset circuit used with the GTP_DUAL tiles in Virtex-5 LXT and SXT devices is not necessary when using the GTX_DUAL tiles in Virtex-5 FXT and TXT devices. The RX elastic buffer reset sequence during an electrical idle condition is available for additional functionality.
During an electrical idle condition, the Clock Data Recovery (CDR) circuit in the receiver can lose lock (“RX Clock Data Recovery,” page 179). To restart the CDR after an electrical idle condition, set the RX_EN_IDLE_RESET_PH, RX_EN_IDLE_RESET_FR, and RX_EN_IDLE_HOLD_CDR attributes to TRUE. These attributes affect both GTX
transceivers in a GTX_DUAL tile. The CDR_PH_ADJ_TIME[4:0] attribute sets the wait time before deassertion of the CDR phase reset and must be left at the default value. The RX_EN_IDLE_RESET_BUF_0 attribute enables a reset sequence for the GTX0 transceiver’s RX elastic buffer and RX_EN_IDLE_RESET_BUF_1 does the same for the GTX1
transceiver. The RX elastic buffer of a GTX transceiver is automatically held in reset and reinitialized after the end of an electrical idle condition on the RX pin pair if the RX_EN_IDLE_RESET_BUF_(0/1) attributes are set to TRUE. The
RX_IDLE_HI_CNT_(0/1) and RX_IDLE_LO_CNT_(0/1) attributes control the timing of the RX elastic buffer reset sequence and must be left at the default values.
RocketIO GTX Transceiver User GuideUG198 (v3.0) October 30, 2009
Chapter 5:Tile Features
Resetting the GTX_DUAL Tile
Each GTX_DUAL tile offers several ways to reset its subcomponents. Table5-8 shows all the different ways of resetting a GTX_DUAL tile, and the subcomponents that are affected by each type of reset.
Table 5-8:
Available Resets Pins and the Components Reset by These Reset Pins
PLLPOWERDOWN(Falling Edge)PRBSCNTRESET0PRBSCNTRESET1RXCDRRESET0RXCDRRESET1RXBUFRESET0RXBUFRESET1ConfigurationGTXRESETRXRESET0RXRESET1TXRESET0TXRESET1Component
GTX-to-Board InterfaceShared Resources
Termination Resistor CalibrationShared PMA PLLPLL Lock DetectionReset ControlPower ControlClockingDRP
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TX PCSFPGA TX Interface8B/10B EncoderTX BufferPRBS GeneratorPolarity Control
TX PMAPISO
TX Pre-emphasisTX OOB & PCITX Driver
RX PCSFPGA RX InterfaceRX Elastic BufferRX Status Control8B/10B DecoderComma Detect and AlignRX LOS State MachineRX PolarityPRBS Checker5x Oversampler
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
Chapter 5:Tile Features
RocketIO GTX Transceiver User Guide
UG198 (v3.0) October 30, 2009
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