基于VHDL的交通灯控制系统的设计

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if (next_state='1') then recount<='1'; state<=yewrsn; sign_state<=\ else

recount<='0'; state<=gewrsn; end if;

elsif (a_m='0' and ena_scan='1') then if (st_transfer='0') then recount<='1'; state<=gewrsn; else

recount<='1'; state<=yewrsn;

sign_state<=\ end if; end if; when yewrsn=>

if (a_m='1' and ena_1hz='1') then if (next_state='1') then recount<='1'; state<=rewgsn;

sign_state<=\ else

recount<='0'; state<=yewrsn; end if;

elsif (a_m='0' and ena_scan='1') then if (st_transfer='0') then recount<='1'; state<=yewrsn; else

recount<='1'; state<=rewgsn;

sign_state<=\ end if; end if; when others=>

state<=rewgsn; recount<='0';

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sign_state<=\ end case; end if; end if; end process;

light<=\ \ \ \ \

red<=light(5 downto 4); yellow<=light(3 downto 2); green<=light(1 downto 0); end;

5.连接各个模块的程序代码 library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity light is

port(reset:in std_logic; clk:in std_logic; a_m:in std_logic; st_butt:in std_logic; recount:out std_logic; next_state:out std_logic;

sign_state:out std_logic_vector(2 downto 0); red:out std_logic_vector(1 downto 0); green:out std_logic_vector(1 downto 0); yellow:out std_logic_vector(1 downto 0); led:out std_logic_vector(24 downto 0)); end;

architecture bhv of light is signal ena_scan_1:std_logic; signal ena_1hz_1:std_logic;

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signal flash_1hz_1:std_logic; signal recount_1:std_logic; signal next_state_1:std_logic;

signal sign_state_1:std_logic_vector(2 downto 0); signal load:std_logic_vector(7 downto 0); component hld1

port(reset:in std_logic; clk:in std_logic; ena_scan:out std_logic; ena_1hz:out std_logic; flash_1hz:out std_logic); end component; component hld2

port(reset:in std_logic; clk:in std_logic; ena_scan:in std_logic; recount:in std_logic;

sign_state:in std_logic_vector(2 downto 0); load:out std_logic_vector(7 downto 0)); end component; component hld3

port(reset:in std_logic; clk:in std_logic; ena_1hz:in std_logic; recount:in std_logic;

load:in std_logic_vector(7 downto 0); led:out std_logic_vector(24 downto 0); next_state:out std_logic); end component; component hld4

port(reset:in std_logic; clk:in std_logic;

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ena_scan:in std_logic; ena_1hz:in std_logic; flash_1hz:in std_logic; a_m:in std_logic; st_butt:in std_logic; next_state:in std_logic; recount:out std_logic;

sign_state:out std_logic_vector(2 downto 0); red:out std_logic_vector(1 downto 0); green:out std_logic_vector(1 downto 0); yellow:out std_logic_vector(1 downto 0)); end component; begin

u1:hld1 port map(reset,clk,ena_scan_1,ena_1hz_1,flash_1hz_1); u2:hld2 port map(reset,clk,ena_scan_1,recount_1,sign_state_1,load); u3:hld3 next_state_1);

u4:hld4 port map(reset,clk,ena_scan_1,ena_1hz_1,flash_1hz_1,a_m, st_butt,next_state_1,recount_1,sign_state_1,red,green,yellow); next_state<=next_state_1; recount<=recount_1; sign_state<=sign_state_1;

end;

port map(reset,clk,ena_1hz_1,recount_1,load,led,

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