DS022-1 (v3.0) March 21, 2014
00Production Product Specification
Features
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Fast, High-Density 1.8V FPGA Family
-Densities from 58k to 4M system gates
-130 MHz internal performance (four LUT levels)-Designed for low-power operation
-PCI compliant 3.3V, 32/64-bit, 33/ 66-MHzHighly Flexible SelectI/O+? Technology
-Supports 20 high-performance interface standards-Up to 804 singled-ended I/Os or 344 differential I/O
pairs for an aggregate bandwidth of > 100 Gb/sDifferential Signalling Support
-LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL-Differential I/O signals can be input, output, or I/O-Compatible with standard differential devices-LVPECL and LVDS clock inputs for 300+ MHz
clocks
Proprietary High-Performance SelectLink?Technology
-Double Data Rate (DDR) to Virtex-E link-Web-based HDL generation methodologySophisticated SelectRAM+? Memory Hierarchy-1Mb of internal configurable distributed RAM-Up to 832Kb of synchronous internal block RAM-True Dual-Port BlockRAM capability
-Memory bandwidth up to 1.66Tb/s (equivalent
bandwidth of over 100 RAMBUS channels)-Designed for high-performance Interfaces to
External Memories-200MHz ZBT* SRAMs-200Mb/s DDR SDRAMs
-Supported by free Synthesizable reference design
*ZBT is a trademark of Integrated Device Technology, Inc.
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High-Performance Built-In Clock Management Circuitry-Eight fully digital Delay-Locked Loops (DLLs)-Digitally-Synthesized 50% duty cycle for Double
Data Rate (DDR) Applications-Clock Multiply and Divide
-Zero-delay conversion of high-speed LVPECL/LVDS
clocks to any I/O standard
Flexible Architecture Balances Speed and Density-Dedicated carry logic for high-speed arithmetic-Dedicated multiplier support
-Cascade chain for wide-input function
-Abundant registers/latches with clock enable, and
dual synchronous/asynchronous set and reset-Internal 3-state bussing
-IEEE 1149.1 boundary-scan logic-Die-temperature sensor diode
Supported by Xilinx Foundation? and Alliance Series?Development Systems
-Further compile time reduction of 50%-Internet Team Design (ITD) tool ideal for
million-plus gate density designs
-Wide selection of PC and workstation platformsSRAM-Based In-System Configuration-Unlimited re-programmabilityAdvanced Packaging Options-0.8mm Chip-scale-1.0mm BGA-1.27mm BGA-HQ/PQ
0.18μm 6-Layer Metal Process100% Factory Tested
质量等级领域:宇航级IC、特军级IC、超军级IC、普军级IC、禁运IC、工业级IC，军级二三极管，功率管等;
应用领域:航空航天、船舶、汽车电子、军用计算机、铁路、医疗电子、通信网络、电力工业以及大型工业设备
祝您:工作顺利，生活愉快!
以赛灵思半导体（深圳）有限公司提供的参数为例，以下为XCV600E7FG676C的详细参数，仅供参考
DS022-1 (v3.0) March 21, 2014Production Product Specification
Virtex?-E 1.8 V Field Programmable Gate Arrays
Table 1: Virtex-E Field-Programmable Gate Array Family Members
DeviceXCV50EXCV100EXCV200EXCV300EXCV400EXCV600EXCV1000EXCV1600EXCV2000EXCV2600EXCV3200E
System Gates71,693128,236306,393411,955569,952985,8821,569,1782,188,7422,541,9523,263,7554,074,387
Logic Gates20,73632,40063,50482,944129,600186,624331,776419,904518,400685,584876,096
CLB Array16 x 2420 x 3028 x 4232 x 4840 x 6048 x 7264 x 9672 x 10880 x 12092 x 138104 x 156
Logic Cells1,7282,7005,2926,91210,80015,55227,64834,99243,20057,13273,008
Differential I/O Pairs
8383119137183247281344344344344
User I/O176196284316404512660724804804804
BlockRAM
Bits65,53681,920114,688131,072163,840294,912393,216589,824655,360753,664851,968
Distributed RAM Bits24,57638,40075,26498,304153,600221,184393,216497,664614,400812,5441,038,336
DS022-1 (v3.0) March 21, 2014Production Product Specification
Virtex?-E 1.8 V FieldProgrammableGateArrays
Virtex-E Device/Package Combinations and Maximum I/O
Table 3: Virtex-E Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins)
XCV50E
CS144PQ240HQ240BG352BG432BG560FG256FG456FG676FG680FG860FG900FG1156
512
176
176
176284
176312
404
444512
512660660660
512660700724
804
804
804
512660
196
260
260316
316404
316404
404
404
404
94158
XCV100E94158
XCV200E94158
158
158
158
158
XCV300E
XCV400E
XCV600E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
DS022-1 (v3.0) March 21, 2014Production Product Specification
Virtex?-E 1.8 V FieldProgrammableGateArrays
DS022-2 (v3.0) March 21, 2014Production Product Specification
Virtex?-E 1.8 V Field Programmable Gate Arrays
RAMB4_S#_S#WEAENARSTA CLKAADDRA[#:0]DIA[#:0]?
Direct paths that provide high-speed connectionsbetween horizontally adjacent CLBs, eliminating thedelay of the GRM.
To AdjacentGRMDOA[#:0]WEBENBRSTB CLKBADDRB[#:0]DIB[#:0]ToAdjacentGRMGRMTo AdjacentGRMDOB[#:0]To AdjacentGRMDirect ConnectionTo AdjacentCLBCLBDirectConnectionTo AdjacentCLBXCVE_ds_007ds022_06_121699Figure 6: Dual-Port Block SelectRAMTable5 shows the depth and width aspect ratios for theblock SelectRAM. The Virtex-E block SelectRAM alsoincludes dedicated routing to provide an efficient interfacewith both CLBs and other block SelectRAMs. Refer toXAPP130 for block SelectRAM timing waveforms.Table 5: Block SelectRAM Port Aspect RatiosWidth124816
Depth409620481024512256
ADDR BusADDR<11:0>ADDR<10:0>ADDR<9:0>ADDR<8:0>ADDR<7:0>
Data BusDATA<0>DATA<1:0>DATA<3:0>DATA<7:0>DATA<15:0>
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Figure 7: Virtex-E Local RoutingGeneral Purpose Routing
Most Virtex-E signals are routed on the general purposerouting, and consequently, the majority of interconnectresources are associated with this level of the routing hier-archy. General-purpose routing resources are located inhorizontal and vertical routing channels associated with theCLB rows and columns and are as follows:?
Adjacent to each CLB is a General Routing Matrix(GRM). The GRM is the switch matrix through whichhorizontal and vertical routing resources connect, andis also the means by which the CLB gains access tothe general purpose routing.
24 single-length lines route GRM signals to adjacentGRMs in each of the four directions.
72 buffered Hex lines route GRM signals to anotherGRMs six-blocks away in each one of the four
directions. Organized in a staggered pattern, Hex linesare driven only at their endpoints. Hex-line signals canbe accessed either at the endpoints or at the midpoint(three blocks from the source). One third of the Hexlines are bidirectional, while the remaining ones areuni-directional.
12 Longlines are buffered, bidirectional wires thatdistribute signals across the device quickly and
efficiently. Vertical Longlines span the full height of thedevice, and horizontal ones span the full width of thedevice.
Programmable Routing Matrix
It is the longest delay path that limits the speed of anyworst-case design. Consequently, the Virtex-E routingarchitecture and its place-and-route software were definedin a joint optimization process. This joint optimization mini-mizes long-path delays, and consequently, yields the bestsystem performance.
The joint optimization also reduces design compilationtimes because the architecture is software-friendly. Designcycles are correspondingly reduced due to shorter designiteration times.
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Local Routing
The VersaBlock provides local routing resources (seeFigure7), providing three types of connections:??
Interconnections among the LUTs, flip-flops, and GRMInternal CLB feedback paths that provide high-speedconnections to LUTs within the same CLB, chainingthem together with minimal routing delay
I/O Routing
Virtex-E devices have additional routing resources aroundtheir periphery that form an interface between the CLB arrayand the IOBs. This additional routing, called the
VersaRing, facilitates pin-swapping and pin-locking, suchthat logic redesigns can adapt to existing PCB layouts.Time-to-market is reduced, since PCBs and other systemcomponents can be manufactured while the logic design isstill in progress.
DS022-2 (v3.0) March 21, 2014Production Product Specification
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