SIV51001-3.5
Altera? Stratix? IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. StratixIV FPGAs are based on the Taiwan Semiconductor
Manufacturing Company (TSMC) 40-nm process technology and surpass all other high-end FPGAs, with the highest logic density, most transceivers, and lowest power requirements.
The StratixIV device family contains three optimized variants to meet different application requirements:
■
Stratix IV E (Enhanced) FPGAs—up to 813,050 logic elements (LEs), 33,294 kilobits(Kb) RAM, and 1,288 18x18 bit multipliers
Stratix IV GX transceiver FPGAs—up to 531,200 LEs, 27,376 Kb RAM, 1,28818x18-bit multipliers, and 48 full-duplex clock data recovery (CDR)-basedtransceivers at up to 8.5Gbps
Stratix IV GT—up to 531,200 LEs, 27,376 Kb RAM, 1,288 18 x 18-bit multipliers,and 48 full-duplex CDR-based transceivers at up to 11.3Gbps
■
■
The complete Altera high-end solution includes the lowest risk, lowest total cost path to volume using HardCopy? IV ASICs for all the family variants, a comprehensive portfolio of application solutions customized for end-markets, and the industry leading Quartus? II software to increase productivity and performance.
fFor information about upcoming Stratix IV device features, refer to the Upcoming
Stratix IV Device Features document.fFor information about changes to the currently published Stratix IV Device Handbook,
refer to the Addendum to the Stratix IV Device Handbook chapter.
This chapter contains the following sections:
■■■■
“Feature Summary” on page1–2“Architecture Features” on page1–6“Integrated Software Platform” on page1–19“Ordering Information” on page1–19
Stratix IV Device HandbookVolume 1January 2016
Chapter 1:Overview for the Stratix IV Device Family
Feature Summary
General PurposeI/O and Memory PLLInterfacePLLGeneral Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDRPLLGeneral PurposeI/O and Memory InterfacePLLGeneral Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDRPLLPLLGeneral Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDRFPGA Fabric(Logic Elements, DSP, Embedded Memory,Clock Networks)PLLPLLGeneral Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDRPLLGeneral PurposeI/O and Memory PLLInterfacePLLGeneral PurposeI/O and Memory InterfacePLLGeneral Purpose I/O and High-Speed LVDS I/O with DPA and Soft-CDRGeneral Purpose I/O and 150 Mbps-1.6 Gbps
LVDS interface with DPA and Soft-CDR
Stratix IV Device HandbookVolume 1
Volume 1Stratix IV Device HandbookTable1–1.StratixIVGX Device Features(Part 2 of 2)
FeatureEP4SGX70
EP4SGX110
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530 Package 0202027027272270202858585151005130516363Option7171715815861598157979F1F1111711111FFF1171177FFFFFF1FFFFF1FFFFFFM9K Blocks(256 x 4626609501,2359361,248
1,28036 bits)M144K Blocks(2048 x 161620223648
6472 bits)Total Memory (MLAB+M9K7,3709,56413,62717,13317,24822,564
27,376+M144K) KbEmbedded Multipliers 384
512
9201,288832
1,0401,0241,02418 x 18 (2)PLLs343436836846
8121246812121212User I/Os (3)
372488
3723724856567474888372444372564
5674567488924
4
289
5644
4
0
0
289564
564
4
0
920
880
920Speed Grade –2?,–2,–2?–2?–2–2–2?–2?
–2?–2?–2?
,,–2,–2??,,–2,,,,–2,(fastest to –3,–3,,
–2,–2,
–2?–2,–2,–2,–2,
–2, –3,–3,–3,–3,,–3,–3–3,–3,–3,–3,,
–2,–2,–2,slowest) (5)–4–4
–3,
–3,–3,
,–3,–3,–3,–3,–3,–4
–4
–4
–4
–3,–4
–4
,–4
–4
–4
–4
–4–4
–4–4
–4–4–4–4
–3,
–3,–3,–3,–3,–2, –3,–4
–4
–4
–4–4–4–4
Notes to Table1–1:
(1)The total number of transceivers is divided equally between the left and right side of each device, except for the devices in the F780 package. These devices have eight transceiver channels located only
on the right side of the device.(2)Four multiplier adder mode.
(3)The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver pins and dedicated configuration pins are not included in
the pin count.(4)Total pairs of high-speed LVDS SERDES take the lowest channel count of RX/TX.
(5)The difference between the Stratix IV GX devices in the –2 and –2x speed grades is the number of available transceiver channels. The –2 device allows you to use the transceiver CMU blocks as
transceiver channels. The –2x device does NOT allow you to use the CMU blocks as transceiver channels. In addition to the reduction of available transceiver channels in the Stratix IV GX –2x device,the data rates in the –2x device are limited to 6.5 Gbps.
Chapter 1:Architecture FeaturesOverview for the Stratix IV Device FamilyChapter 1:Overview for the Stratix IV Device FamilyArchitecture Features
Stratix IV Device Handbook
Volume 1
Chapter 1:Overview for the Stratix IV Device Family
Architecture Features
Table1–8 lists the resource counts for the Stratix IV GT devices.Table1–8.Stratix IV GT Device Package Options (1), (2)
Device
Stratix IV GT 40G DevicesEP4S40G2EP4S40G5
Stratix IV GT 100G DevicesEP4S100G2EP4S100G3EP4S100G4EP4S100G5
F40——H40 (4), (5)
—F45F45F45
F40H40 (4), (5)
——
1517Pin
(40mmx40mm) (3)
1932Pin(45mmx45mm)
Stratix IV Device HandbookVolume 1
相关推荐：
loading