Configuration Packets
If it is a known-vendor command, the SPI read command needs to be loaded to GENERAL2.
In case of SPI, the general register contains an 8-bit command plus a 24-bit address. See Table5-42.Table 5-42:
SPI General Register Example
gen1[15:0]addr[15:0]
gen2[15:0]rd_cmd[7:0], addr[23:16]
BPI has a 26-bit address (there are 6 don’t care bits). See Table5-43.Table 5-43:
BPI General Register Example
gen1[15:0]addr[15:0]
gen2[15:0]xxxxxx, address[25:16]
MODE Register
The MODE register contains the mode setting (twobits for bus width, threebits for mode, and eightbits for vsel), which can be used for the reboot. The default is the original pin setting.
This register is cleared in the same way as General registers, that is they can only be cleared by bus_reset0 but NOT by reboot_rst (bus_reset = bus_reset || reboot_rst). See Table5-44.Table 5-44:
NameRESERVEDRESERVEDNEW_MODE
MODE Registers Description
Bits151413
Reserved.Reserved.
0: Physical mode, ignore bit[10:0] (default).1: Bitstream mode, use bit[10:0], required for MultiBoot and Fallback.The buswidth setting to reboot.SPI:00: by 101: by 210: by 4
Mode setting required for MultiBoot and Fallback. Enabled by NEW_MODE.bit [10]: Reservedbit [9]: BOOTMODE <1>bit [8]: BOOTMODE <0>
Description
Default000
BUSWIDTH12:1100 (SPI by1)
BOOTMODE10:8001
BOOTVSEL7:0The vsel setting to reboot.Read only.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 5:Configuration Details
iMPACT Access to Device Identifier
The iMPACT software in ISE 10.1 (and later) tools can also read the device DNA value. readDna -p
Bitstream Compression
By default, FPGA bitstreams are uncompressed. However, Spartan-6 FPGAs support basic bitstream compression. The compression is fairly simple, yet effective for some
applications. The ISE bitstream generator software examines the FPGA bitstream for any duplicate configuration data frames. These duplicates occur often in these situations:??
FPGA designs with unused block RAM or hardware multipliers.
FPGA designs with low logic utilization, such as when most of the FPGA array isempty.
The ISE software can then generate a compressed FPGA bitstream. As the FPGA configures, the internal configuration controller copies the redundant data frame to multiple locations. Compression is not supported for encrypted bitstreams.
The amount of compression is non-deterministic. Changes to the source FPGA design can cause the size of the compressed bitstream to grow. Sparse, mostly empty FPGA designs have the greatest overall compression factor. Similarly, FPGA designs with an empty column of block RAM have a high compression factor.The overall benefits of a compressed bitstream are:???
Smaller memory footprint.
Faster programming time for nonvolatile memory.Faster configuration time.
Compression is enabled using the BitGen option -g compress.
Parallel Platform Flash PROMs offer their own compression mechanisms. For more details, see the “XCFxxP Decompression and Clock Options” chapter in UG161, Platform Flash PROM User Guide.
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Chapter 2:Configuration Interface Basics
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Chapter 3:Boundary-Scan and JTAG Configuration
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Chapter 5:Configuration Details
Configuration Watchdog Timer Register
The configuration watchdog timer (CWDT) register stores the value of the number of clock cycles that the FPGA will wait before the watchdog time-out (in which SYNCWORD is not received). The default is 64k clock cycles. The minimum value is 16h'0201.Table 5-39:
Bits[15:0]
CWDT Register
Value16h'ffff
HC_OPT_REG Register
The HC_OPT_REG register can only be reset to default by por_b.Table 5-40:
NameINIT_SKIPRESERVED
HC_OPT_REG Description
Bits65:0
Description
0: Do not skip initialization.1: Skip initialization.Reserved.
Default0011111
GENERAL Registers 1, 2, 3, 4, and 5
GENERAL1 and GENERAL2 registers are used to store loadable multiple configuration addresses for SPI and BPI.
GENERAL3 and GENERAL4 registers have a similar function as GENERAL1 and
GENERAL2, except that GENERAL3 and GENERAL4 store the golden bitstream address instead of the MultiBoot address.
The GENERAL5 register is a 16-bit register that allows users to store and access any extra information desired for the fail-safe scheme. These register contents are untouched during a soft reboot.
These registers are set by the bitstream. BitGen can be instructed not to write to these registers using the -g next_config_register_write:Disable command. This allows the ability to store user data in the FPGA between re-configuration attempts.Table 5-41:
NameGENERAL1GENERAL2GENERAL3GENERAL4GENERAL5
General Registers
Bits[15:0][15:0][15:0][15:0][15:0]
Description
The lower half of the multiple boot address.15:8 – SPI opcode.
7:0 – Higher half of the boot address.
The lower half of the golden bitstream address.15:8 – SPI opcode.
7:0 – Higher half of the golden boot address.The user-defined scratchpad register.
If the second configuration needs a previously unknown SPI vendor command, the new vendor command has already been loaded in GENERAL2 from the bitstream by this point.
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
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