多周期MIPS CPU实验报告

input[31:0]WD3, output[31:0]RD1,RD2 );

reg[31:0]regs[0:31]; integer i; initial begin

for(i=0;i<32;i=i+1) regs[i]=0; end

assign RD1=regs[A1]; assign RD2=regs[A2]; always@(posedge clk) begin

if(WE3) regs[A3]<=WD3; end endmodule

module SignExtend( input[15:0] i_num, outputreg[31:0] o_num );

initialbegin o_num =0; end

always@(*) begin

o_num ={{16{i_num[15]}}, i_num[15:0]}; end endmodule

module ALU(A, B, ALUOp, zero, result); input[31:0] A, B; input[2:0] ALUOp; outputreg zero;

outputreg[31:0] result; initialbegin result =0; zero=0; end

always@(*)begin case(ALUOp)

3'b000:begin result = A + B;zero=0;end 3'b001:begin result = A - B; zero=0;end

3'b010:begin result = B - A;zero=0;end 3'b011:begin result = A | B;zero=0;end 3'b100:begin result = A & B;zero=0;end 3'b101:begin result =~A & B;zero=0;end

3'b110:begin result =(~A & B)|(A &~B);zero=0;end 3'b111:begin

if(A>32'b0) zero=1'b1; else zero=0; end

default:begin result =0; zero=0;end endcase end endmodule

module Mux3( input[31:0]A,B,C, input[1:0]S, outputreg[31:0]D );

always@(*) case(S) 2'b00:D<=A; 2'b01:D<=B; 2'b10:D<=C; endcase endmodule

module CU( input clk,rst_n, input[5:0]Op,Funct, outputreg

PCWrite,Branch,ALUSrcA,RegWrite,MemtoReg,RegDst,lorD,MemWrite,IRWrite,

outputreg[2:0]ALUOp,

outputreg[1:0]ALUSrcB,PCSrc );

parameter s0=4'd0; parameter s1=4'd1; parameter s2=4'd2; parameter s3=4'd3; parameter s4=4'd4; parameter s5=4'd5; parameter s6=4'd6; parameter s7=4'd7;

parameter s8=4'd8; parameter s9=4'd9; parameter s10=4'd10; parameter s11=4'd11; parameter s12=4'd12; parameter Rtype=6'b000000; parameter ADDI=6'b001000; parameter LW=6'b100011; parameter SW=6'b101011; parameter BGTZ=6'b000111; parameter J=6'b000010; reg[3:0]curr_state; reg[3:0]next_state;

always@(posedge clk ornegedge rst_n) begin if(~rst_n) curr_state<=s0; else

curr_state<=next_state; end

always@(*) begin

case(curr_state) s0:next_state=s12; s12:next_state=s1; s1:begin

if(Op==LW||Op==SW) next_state=s2; if(Op==Rtype) next_state=s6; if(Op==BGTZ) next_state=s8; if(Op==ADDI) next_state=s9; if(Op==J) next_state=s11; end s2:begin

if(Op==LW) next_state=s3; if(Op==SW) next_state=s5; end

s3:next_state=s4; s4:next_state=s0; s5:next_state=s0; s6:next_state=s7; s7:next_state=s0; s8:next_state=s0; s9:next_state=s10; s10:next_state=s0;

s11:next_state=s0; endcase end

always@(posedge clk ornegedge rst_n) begin if(~rst_n) begin lorD=0; ALUSrcA=0; ALUSrcB=2'b01; ALUOp=3'b000; PCSrc=2'b00; IRWrite=1; PCWrite=1; Branch=0; RegWrite=0; MemtoReg=0; RegDst=0; MemWrite=0; end else

case(next_state)

s0:begin//PCWrite,Branch,ALUSrcA,RegWrite,MemtoReg,RegDst,lorD,MemWrite,IRWrite,

lorD=0;//[2:0]ALUOp,

ALUSrcA=0;//[1:0]ALUSrcB,PCSrc ALUSrcB=2'b01; ALUOp=3'b000; PCSrc=2'b00; IRWrite=1; PCWrite=1; Branch=0; RegWrite=0; MemtoReg=0; RegDst=0; MemWrite=0; end s12:begin IRWrite=1; PCWrite=0; end s1:begin ALUSrcA=0; ALUSrcB=2'b11;