FPGA可编程逻辑器件芯片EP3C120F484C8N中文规格书

3.Intel Agilex I/O TerminationUG-20214 | 2021.04.05

3.1.4.2.3. OCT Intel FPGA IP ArchitectureFigure 40.

OCT IP Top-Level Diagram

This figure shows the top-level diagram of the OCT IP.OCT Intel? FPGA IPPadrzqin

OCT PadTable 37.OCT IP Components

Component

Description

??

Dual-purpose pin.

When used with OCT, the pin connects to an external reference resistor to calculate thecalibration codes to implement the required impedance.

RZQ pin

OCT blockGenerates and sends calibration code words to the I/O buffer blocks.

RZQ Pin

There are two RZQ pins in each GPIO bank. The RZQ pin shares the same VCCIO supplywith the I/O bank where the pin is located.

RZQ pins are dual-purpose pins. If the pins are not connected to the OCT block, youcan use the pins as regular I/O pins. When you use the RZQ pin for OCT calibration,the RZQ pin connects the OCT block to ground through an external 240 ? resistor witha precision of ±1 %.

OCT Block

The OCT block is a component that generates calibration codes to terminate the I/Os.There are two OCT blocks in each GPIO bank.

During calibration, the OCT matches the impedance seen on the external resistorthrough the rzqin port. Then, the OCT block generates calibration code words andsends to the I/O buffer through ser_data ports.

Power-Up Mode Interfaces

The OCT IP in power-up mode has two main interfaces:??

One input interface connecting the FPGA RZQ pad to the OCT blockOne output which connects to I/O buffers

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