SelectMAP Configuration Interface
X-Ref Target - Figure 2-8PROGRAM_B(3)INIT_BCCLK(1)(5)(11)CSI_B(2)(4)(12)RDWR_B(6)(7)Byte 1(8)Byte n(10)(9)D[0:n]Byte 0DONEUG380_c2_08_042909Figure 2-8:Continuous x8 or x16 SelectMAP Data Loading
Notes relevant to Figure2-8:1.2.
CSI_B signal can be tied Low if there is only one device on the SelectMAP bus. If CSI_Bis not tied Low, it can be asserted at any time.
RDWR_B can be tied Low if readback is not needed. RDWR_B should not be toggledafter CSI_B has been asserted because this triggers an ABORT. See SelectMAP ABORT, page157.
The Mode pins are sampled when INIT_B goes High.
RDWR_B should be asserted before CSI_B to avoid causing an abort.CSI_B is asserted, enabling the SelectMAP interface.
The first byte is loaded on the first rising CCLK edge after CSI_B is asserted.The configuration bitstream is loaded one byte per rising CCLK edge.After the startup command is loaded, the device enters the startup sequence.The startup sequence lasts a minimum of eight CCLK cycles (see Startup (Step8) inChapter5).
3.4.5.6.7.8.9.
10.The DONE pin goes High during the startup sequence. Additional CCLKs can be
required to complete the startup sequence. (See Startup (Step8) in Chapter5.)11.After configuration has finished, the CSI_B signal can be deasserted.12.After the CSI_B signal is deasserted, RDWR_B can be deasserted.13.The data bus can be x8 or x16.
Non-Continuous SelectMAP Data Loading
Non-continuous data loading is used in applications where the configuration controller cannot provide an uninterrupted stream of configuration data—for example, if the controller pauses configuration while it fetches additional data.
Configuration can be paused in two ways: by deasserting the CSI_B signal (Free-Running CCLK method, Figure2-9) or by halting CCLK (Controlled CCLK method, Figure2-10). The only time that the CSI_B signal must NOT be deasserted is during the loading of the sync word or within two CCLK cycles after the loading of the sync word.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 2:Configuration Interface Basics
X-Ref Target - Figure 2-9PROGRAM_B(2)INIT_B(4)(5)(6)(7)(8)(9)(10)(11)(12)(13)CCLK(3)CSI_BDATA[0:n](1)RDWR_BUG380_c2_09_042909Figure 2-9:Non-Continuous SelectMAP Data Loading with Free-Running CCLK
Notes relevant to Figure2-9:1.
RDWR_B is driven Low by the user, setting the D[0:n] pins as inputs for configuration. RDWR_B can be tied Low if readback is not needed. RDWR_B should not be toggledafter CSI_B has been asserted because this triggers an ABORT. See SelectMAP ABORT, page157. CSI_B cannot be deasserted during the sync word.The device is ready for configuration after INIT_B toggles High.
The user asserts CSI_B Low, enabling the SelectMAP data bus. CSI_B signal can be tied Low if there is only one device on the SelectMAP bus. If CSI_B is not tied Low, it can be asserted at any time.
A byte is loaded on the rising CCLK edge. The data bus can be x8 or x16 wide.A byte is loaded on the rising CCLK edge.The user deasserts CSI_B, and the byte is ignored.The user deasserts CSI_B, and the byte is ignored.A byte is loaded on the rising CCLK edge.A byte is loaded on the rising CCLK edge.
2.3.
4.5.6.7.8.9.
10.The user deasserts CSI_B, and the byte is ignored.11.A byte is loaded on the rising CCLK edge.12.A byte is loaded on the rising CCLK edge.13.A byte is loaded on the rising CCLK edge.
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Serial Configuration Interface
2.3.4.
DOUT should be connected to the DIN of the downstream FPGA for daisy-chainedconfiguration modes.
The CCLK net requires Thevenin parallel termination. For more details, see BoardLayout for Configuration Clock (CCLK), page56.
The DONE pin is by default an open-drain output with an internal pull-up. Anadditional external pull-up is recommended. The DONE pin has a programmableactive driver that can be enabled via the BitGen option -g DriveDone.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor isrecommended.
The SPI control pins, CSO_B and MOSI, toggle during serial configuration.VFS is present in 6SLX75/T, 6SLX100/T, and 6SLX150/T devices, and is used foreFUSE programming. See eFUSE, page93 for more details.
VBATT is present in 6SLX75/T, 6SLX100/T, and 6SLX150/T devices, and is the powersource for AES key storage. If AES encryption is unused, VBATT can be tied to eitherVCCAUX or ground, or left unconnected.
If VCCO_2 is 1.8V, VCCAUX must be 2.5V. If VCCO_2 is 2.5V or 3.3V, VCCAUX can beeither 2.5V or 3.3V.
5.6.7.8.
9.
10.The SUSPEND pin should be Low during power up and configuration. If the Suspend
feature is not used, the SUSPEND pin must be connected to ground.
Serial Configuration Data Timing
Figure2-4 shows how configuration data is clocked into Spartan-6 devices in Slave Serial and Master Serial modes.
X-Ref Target - Figure 2-4PROGRAM_BINIT_BMaster CLK begins hereCCLKMaster DINBIT 0BIT 1BIT nBIT n+1Master DOUTData bits clocked out on falling edge of CCLKDONEUG380_c2_04_0121012Figure 2-4:
Notes relevant to Figure2-4:1.2.3.
Serial Configuration Clocking Sequence
Bit 0 represents the MSB of the first byte. For example, if the first byte is 0xAA(1010_1010), bit 0=1, bit 1=0, bit 2=1, etc.
For Master configuration mode, CCLK does not transition until after the Mode pins are sampled, as indicated by the arrow.
CCLK can be free-running in Slave Serial mode.
Spartan-6 FPGA Configuration User GuideUG380 (v2.11) March 22, 2019
Chapter 2:Configuration Interface Basics
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
Chapter 3:Boundary-Scan and JTAG Configuration
Spartan-6 FPGA Configuration User Guide
UG380 (v2.11) March 22, 2019
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