Chapter 1:Package Overview
Pin Definitions
Table1-5 lists the pin definitions used in Zynq-7000SoC packages.
Note:There are dedicated general purpose user I/O pins listed separately in Table1-5. There are
also multi-function pins where the pin names start with either IO_LXXY_ZZZ_# or IO_XX_ZZZ_#, where ZZZ represents one or more functions in addition to being general purpose user I/O. If not used for their special function, these pins can be user I/O.
Table 1-5:Zynq-7000SoC Pin Definitions
Type
Direction
Description
Most user I/O pins are capable of differential signaling and can be implemented as pairs. The top and bottom I/O pins are always single ended. Each user I/O is labeled IO_LXXY_#, where:
?IO indicates a user I/O pin.
?L indicates a differential pair, with XX a unique pair inthe bank and Y = [P|N] for the positive/negative sides ofthe differential pair.?# indicates a bank number.
Pin NameUser I/O Pins
IO_LXXY_#IO_XX_#
Dedicated
Input/Output
Configuration Pins
For more information about these pins, see the Configuration Pin Definitions table in the 7SeriesFPGAsConfiguration User Guide (UG470) [Ref10]. See also the Boot and Configuration chapter in the Zynq-7000SoC Technical Reference Manual (UG585)[Ref1].DONE_0INIT_B_0PROGRAM_B_0TCK_0TDI_0TDO_0TMS_0
Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)Dedicated(1)
Bidirectional
Active High, DONE indicates successful completion of configuration.
Bidirectional Active Low, indicates initialization of configuration (open-drain)memory.
InputInputInputOutputInput
Active Low, asynchronous reset to configuration logic.JTAG clock.JTAG data input.JTAG data output.JTAG mode select.
This pin selects the preconfiguration I/O standard type for the dedicated configuration bank 0. If the VCCO for bank 0 is 2.5V or 3.3V, then this pin must be connected to VCCO_0. If the VCCO for bank 0 is less than or equal to 1.8V, then this pin should be connected to GND.
connected correctly. See the Configuration Bank Voltage Select section in the 7Series FPGAs Configuration User Guide (UG470) [Ref10] for more information.
CFGBVS_0Dedicated(1)Input
Note:To avoid device damage, this pin must be
Zynq-7000SoC Packaging GuideUG865 (v1.8.1) June 22, 2018
Chapter 1:Package Overview
Zynq-7000SoC Packaging GuideUG865 (v1.8.1) June 22, 2018
Chapter 1:Package Overview
Table 1-5:
Zynq-7000SoC Pin Definitions (Cont’d)
Type
Direction
Description
Pin Name
Multi-gigabit Serial Transceiver Pins (GTXE2 and GTPE2)
For more information on the GTXE2 pins see the Pin Description and Design Guidelines section in the 7Series FPGAs GTX/GTH Transceivers User Guide (UG476) [Ref11]. The GTPE2 pins are described in the Pin Description and Design Guidelines section of the 7Series FPGAs GTP Transceivers User Guide (UG482) [Ref12].MGTXRXP[0:3] or MGTPRXP[0:3]MGTXRXN[0:3] or MGTPRXN[0:3]MGTXTXP[0:3] orMGTPTXP[0:3]MGTXTXN[0:3] orMGTPTXN[0:3]MGTAVCC_G#(7)MGTAVTT_G#(7)MGTVCCAUX_G#(7)MGTREFCLK0/1PMGTREFCLK0/1NMGTAVTTRCAL
DedicatedDedicatedDedicatedDedicatedDedicatedDedicatedDedicatedDedicatedDedicatedDedicated
InputInputOutputOutputInputInputInputInputInputN/A
Positive differential receive port.Negative differential receive port.Positive differential transmit port.Negative differential transmit port.
1.0V analog power-supply pin for the receiver and transmitter internal circuits.
1.2V analog power-supply pin for the transmit driver.1.8V auxiliary analog Quad PLL (QPLL) voltage supply for the GTXE2 transceivers only.
Positive differential reference clock for the transceivers.Negative differential reference clock for the transceivers.GTXE2 precision reference resistor pin for internal calibration termination. Not used for the XC7Z007S, XC7Z010, XC7Z012S, XC7Z014S, XC7Z015, or XC7Z020 devices.
Precision reference resistor pin for internal calibration termination.
MGTRREFDedicatedInput
Other Pins
These are the clock capable I/Os driving BUFRs, BUFIOs, BUFGs, and MMCMs/PLLs. In addition, these pins can drive the BUFMR for multi-region BUFIO and BUFR support. These pins become regular user I/Os when not needed as a clock. When connecting a single-ended clock to the differential CC pair of pins, it must be connected to the positive (P) side of the pair. The MRCC (multi-region) pins, when used as single-region resource, can drive four BUFIOs and four BUFRs in a single bank.
These are the clock capable I/Os driving BUFRs, BUFIOs, BUFGs, and MMCMs/PLLs. These pins become regular user I/Os when not needed for clocks. When connecting a single-ended clock to the differential CC pair of pins, it must be connected to the positive (P) side of the pair. The SRCC (single-region) pins can drive four BUFIOs and four BUFRs in a single bank.
MRCCMulti-functionInput
SRCCMulti-functionInput
Zynq-7000SoC Packaging GuideUG865 (v1.8.1) June 22, 2018
Chapter 2:Zynq-7000SoC Package Files
Zynq-7000SoC Packaging GuideUG865 (v1.8.1) June 22, 2018
Chapter 5:Thermal Specifications
Support for Thermal Models
Table5-1 provides the traditional thermal resistance data for Zynq-7000SoC devices. These resistances are measured using a prescribed JEDEC standard that might not necessarily reflect the user’s actual board conditions and environment. The quoted θJA and θJC
numbers are environmentally dependent, and JEDEC has traditionally recommended that these be used with that awareness. For more accurate junction temperature predictions, a system-level thermal simulation might be required.
Though Xilinx continues to support this figure of merit data, for Zynq-7000SoC devices, boundary conditions independent thermal resistor network (Delphi) models are offered. These compact models seek to capture the thermal behavior of the packages more
Zynq-7000SoC Packaging GuideUG865 (v1.8.1) June 22, 2018
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